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BIDES: A BIST design expert system

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Abstract

BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.

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Authors and Affiliations

  1. Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University, 24061, Blacksburg, VA, USA

    Kwanghyun Kim, Joseph G. Tront & Dong S. Ha

Authors
  1. Kwanghyun Kim
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  2. Joseph G. Tront
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  3. Dong S. Ha
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Now with Samsung Electronics, Chase Plaza Bldg. SF, 34–35 Jeong-Dong, Choong-Ku, Seoul, Korea.

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Kim, K., Tront, J.G. & Ha, D.S. BIDES: A BIST design expert system. J Electron Test 2, 165–179 (1991). https://doi.org/10.1007/BF00133501

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  • DOI: https://doi.org/10.1007/BF00133501

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