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Transparent random access memory testing for pattern sensitive faults

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Abstract

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

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Authors and Affiliations

  1. Research Laboratory of Design and Testing of Computer Hardware Department of Electrical, Computer and Systems Engineering, Boston University, 02215, Boston, MA, USA

    M. G. Karpovsky & V. N. Yarmolik

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  1. M. G. Karpovsky
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  2. V. N. Yarmolik
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This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.

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Karpovsky, M.G., Yarmolik, V.N. Transparent random access memory testing for pattern sensitive faults. J Electron Test 9, 251–266 (1996). https://doi.org/10.1007/BF00134690

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  • DOI: https://doi.org/10.1007/BF00134690

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