Abstract
The emergence of the IEEE 1149.1 boundary scan standard facilitates structured approaches for board partitioning, allowing test generation and execution on localized logic clusters. This article discusses a study conducted on 1149.1 board designs to examine issues associated with board-level Automatic Test-Pattern Generation (ATPG) and diagnostics.
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A. Halliday, G. Young, and A. Crouch, “Prototype testing simplified by scannable buffers and latches,” Proc. Inter. Test Conf., 1989.
IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, May 21, 1990.
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Sterba, D., Halliday, A. & McClean, D. ATPG and diagnostics for boards implementing boundary scan. J Electron Test 2, 89–98 (1991). https://doi.org/10.1007/BF00134945
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DOI: https://doi.org/10.1007/BF00134945