Scan test architectures for digital board testers

Abstract

Boundary scan is a method of implementing test access to the terminals of a component, cluster, or board. Although substituting boundary scan access for direct tester access to these terminals does not alter the concept of digital testing, the replacement of parallel test vectors by serial data streams requires tester support for serial data.

This article first considers the problems posed by boundary scan sequences, which are long and contain meaningful vector data, constant data, and irrelevant, or “don't care” bits, arbitrarily interspersed. We use the model of meaningful data within a “frame” of constant or irrelevant bits as a means of handling vector data efficiently, and we propose the sequencing and control features of the general-purpose digital tester as an efficient way to implement these frames. Using a specific example, we show that the performance achieved and the data storage resources required compare favorably to approaches based on special-purpose framing hardware.