Abstract
The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.
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Dervisoglu, B.I. Features of a Scan and Clock Resource chip for providing access to board-level test functions. J Electron Test 2, 107–115 (1991). https://doi.org/10.1007/BF00134947
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DOI: https://doi.org/10.1007/BF00134947