Abstract
We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain “minimal” and “maximal” test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.
Similar content being viewed by others
References
W.H. Debany, “On using the fanout-free substructure of general combinational networks,” Ph.D. Dissertation, Syracuse University, Syracuse, NY, December 1985.
2.J.P. Hayes, “On realizations of Boolean functions requiring a minimal or near-minimal number of tests,” IEEE Transactions on Computers, vol. C-20, pp. 1506–1513, December 1971.
M.A. Breuer and A.D. Friedman, Diagnosis & Reliable Design of Digital Systems, Rockville, MD, Computer Science Press, 1976.
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, NY, 1990.
J.L. Carter, S.F. Dennis, V.S. Iyengar, B.K. Rosen, “ATPG via random pattern simulation,” Proceedings, International Symposium on Circuits and Systems (ISCAS), pp. 683–686, 1985.
J.H. Aylor, J.P. Cohoon, E.L. Feldhousen, B.W. Johnson, “Compacting randomly generated test sets,” Proceedings, International Conference on Computer Design (ICCD), pp. 153–156, 1990.
S.M. Reddy, “Easily testable realizations for logic functions,” IEEE Transactions on Computers, vol. C-21, pp. 1183–1188, November 1972.
C.D. Weiss, “Bounds on the length of terminal stuck-fault tests,” IEEE Transactions on Computers, vol. C-21, pp. 305–309, March 1972.
S.B. Akers, “Universal test sets for logic networks,” IEEE Transactions on Computers, vol C-23, pp. 835–839, September 1973.
I. Berger and Z. Kohavi, “Fault detection in fanout-free combinational networks,” IEEE Transactions on Computers, vol. C-23, pp. 908–914, October 1973.
J.P. Hayes, “Path complexity of logic networks,” IEEE Transactions on Computers, vol. C-27, pp. 459–462, May 1978.
M.G. Karpovsky, “Universal tests detecting input/output faults in almost all devices,” Proceedings, (dy1982) IEEE International Test Conference, pp. 52–57.
M.G. Karpovsky and L.B. Levitin, “Universal testing of computer hardware,” in Spectral Techniques and Fault Detection, M.G. Karpovsky (Ed.), Academic Press, Orlando, FL, 1985.
B. Krishnamurthy and S.B. Akers, “On the complexity of estimating the size of a test set,” IEEE Transactions on Computers, vol. C-33, pp. 750–753, August 1984.
S.B. Akers and B. Krishnamurthy, “Test counting: An analysis tool for VLSI testing,” Technical Report CR-86-55, Tektronix Computer Research Laboratory, November 1986.
S.B. Akers and B. Krishnamurthy, “Test counting: A tool for VLSI tesing,” IEEE Design & Test of Computers, vol. 6, pp. 58–77, October 1989.
J.P. Hayes and A.D. Friedman, “Test point placement to simplify fault detection,” IEEE Transactions on Computers, vol. C-24, pp. 727–735, July 1974.
O.H. Ibarra and S.K. Sahni, “Polynomially complete fault detection problems,” IEEE Transactions on Computers, vol. C-25, pp. 242–249, March 1975.
H. Fujiwara and S. Toida, “The complexity of fault detection problems for combinational logic circuits,” IEEE Transactions on Computers, vol. C-31, pp. 555–560, June 1982.
The TTL Data Book for Design Engineers, 2nd Ed., Texas Instruments (TI), 1976.
Bipolar Microprocessor Logic and Interface Data Book, Advanced Micro Devices (AMD), 1985.
A.V. Aho, J.E. Hopcroft, J.D. Ullman, Data Structures and Algorithms, Addison-Wesley, Reading, MA, 1983.
J.P. Hayes, “A NAND model for fault diagnosis in combinational logic networks,” IEEE Transactions on Computers, vol. C-20, pp. 1496–1506, December 1971.
F. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN,” Proceedings, International Symposium on Circuits and Systems (ISCAS), 1985.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Debany, W.H., Hartmann, C.R.P. Bounds on the sizes of irredundant test sets and sequences for combinational logic networks. J Electron Test 2, 325–338 (1991). https://doi.org/10.1007/BF00135228
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00135228