Abstract
This is an application-oriented article on I DDQ to guide test engineers to a pragmatic method of implementing I DDQ . This article focuses on different aspects of I DDQ testing; quality, reliability, and test implementation. A description of I DDQ is presented, with different practical methods of implementing it, with empirical reliability data of I DDQ failures, and with empirical burn-in data identifying potential yield benefits. Employing I DDQ testing on digital CMOS technology, the user obtains a product with greater reliability. The data presented within this article, along with increasing customer focus on zero defects, clearly support I DDQ implementation.
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References
P. Weiss, “Do we meet world-class quality standards?,” Computer Design/News Edition, pp. 1–23, September 10, 1990.
B. Rayner, “Market driven quality: IBM's six sigma crusade,” Electronic Business, pp. 68–76, October 15, 1990.
L.K. Horning, J.M. Soden, R.R. Fritzemier, and C.F. Hawkins, ‘Measurements of quiescent power supply current for CMOS ICs in production testing’, Proc. Int. Test Conf., pp. 300–309, September 1987.
J.A. Segura, V.H. Champac, R. Rodriguez, J.A. Rubio, and J. Figueras, “On current testing of gate oxide short failure in static memory cell,” Internal Report, Department of Engineering, University of Barcelona, Spain.
M. Lane and S. McEuen, “I DDQ : A method for detecting potential warranty returns,” Ford Microelectronics Inc., Internal Report, August 27, 1990.
J. Soden and C. Hawkins, “Test considerations for gate oxide shorts in CMOS ICs,” IEEE Design & Test, pp. 56–64, August 1986.
C. Hawkins and J. Soden, “Reliability and electrical properties of gate oxide shorts in CMOS ICs,” Proc. Int. Test Conf., pp. 443–451, 1986.
J. Soden and C. Hawkins, “Reliability of CMOS ICs with gate oxide shorts,” Semiconductor Int., pp. 240–245, May 1987.
J. Soden, R. Treece, M. Taylor, and C. Hawkins, “CMOS IC stuck-open fault electrical effects and design considerations,” Proc. Int. Test Conf., 1989.
C. Hawkins, J. Soden, R. Fritzemier, and L. Horning, “Quiescent power supply current measurements for CMOS IC defect detection,” IEEE Trans. on Industrial Electronics, vol. 36, pp. 211–218, 1989.
M. Keating and D. Meyer, “A new approach to dynamic I DD testing,” Proc. Int. Test Conf., pp. 316–321, 1987.
C. Crapuchettes, “Testing CMOS I DD on large devices,” Proc. Int. Test Conf., pp. 310–315, 1987.
W. Maly and P. Nigh, “Built-in current testing feasibility study,” Proc. ICCAD, pp. 340–343, 1989.
W. Mao, R. Gulati, D. Goel, and M. Ciletti, “Quietest: A quiescent current testing methodology for detecting leakage faults,” Proc. ICCAD, pp. 280–283, 1990.
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McEuen, S.D. Reliability benefits of I DDQ . J Electron Test 3, 327–335 (1992). https://doi.org/10.1007/BF00135336
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DOI: https://doi.org/10.1007/BF00135336