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Algorithms for I DDQ measurement based diagnosis of bridging faults

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Abstract

In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I DDQ measurement based testing.

Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm.

In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I DDQ measurements.

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References

  1. F.J. Ferguson and J.P. Shen, “Extraction and simulatio of realistic faults using inductive fault analysis,” in Proc. 1988 Int. Test Conf., pp. 475–484, September 1988.

  2. F.J. Ferguson and J.P. Shen, “A CMOS fault extractor for inductive fault analysis,” IEEE Trans. on Comput.-Aided Design, vol. 7, pp. 1181–1194, November 1988.

    Google Scholar 

  3. J. Soden and C. Hawkins, “Test considerations for gate oxide shorts in CMOS ICs,” in IEEE Design & Test of Comput., pp. 56–64, August 1986.

  4. D. Feltman, P.J. Nigh, L.R. Carley and W. Maly, “Current sensing for built-in testing of CMOS circuits,” 1988 Int. Conf. on Computer-Aided Design, pp. 454–457, Rye Brook, NY, October 1988.

  5. P. Nigh and W. Maly, “Test generation for current testing,” IEEE Design and Test of Computers, pp. 26–38, February 1990.

  6. W. Mao, R.K. Gulati, D.K. Goel, M.D. Ciletti, “QUIETEST: A quiescent current testing methodology for detecting leakage faults,” in Proc. 1990 IEEE Int. Conf. on Computer-Aided Design, pp. 289–283, November 1990.

  7. R.C. Aitken, “Fault location with current monitoring,” IEEE Int. Test Conf., pp. 623–632, October 1991.

  8. S. Chakravarty and M. Lu Liu, “Algorithms for current monitor based diagnosis of bridging and leakage faults,” Tech. Rep. No. 92-05, Department of Computer Science, State University of New York, Buffalo, NY 14260.

  9. F. Brglez and H. Fujiwara, “A Neutral netlist of 10 combinational benchmark circuits and a target translator in fortran,” special session on ATPG and Fault simulation, IEEE Int. Symposium on Circuits and Systems, 1985.

  10. F.J. Ferguson and T. Larabee, “Test pattern generation for realistic bridging faults in CMOS ICs,” IEEE Int. Test Conf., pp. 492–499, October 1991.

  11. M. Abramovici, “A hierarchical, path-oriented approach to fault diagnosis in modular combinational circuits,” IEEE Trans. on Comput., vol. C-31, pp. 672–677, July 1982.

    Google Scholar 

  12. M. Abramovici and M.A. Breuer, “Multiple fault diagnosis of MOS Combinational Networks,” IEEE Trans. on Comput., vol. C-29, pp. 451–460, June 1980.

    Google Scholar 

  13. H. Cox and J. Rajski, “A method for fault analysis for test generation and fault diagnosis,” IEEE Trans. on Comput.-Aided Design, vol. 7, pp. 813–833, July 1988.

    Google Scholar 

  14. Y.M. El-Ziq and S.Y.H. Su, “Fault diagnosis of MOS combinational networks,” IEEE Trans. on Comput., vol. C-31, February 1982, pp. 129–139.

    Google Scholar 

  15. J. Richman, K. Bowden, “The modern fault dictionary,” in Proc. Int. Test Conf., pp. 696–702, 1985, September 1985.

  16. J. Waicukauski and E. Lindbloom, “Failure diagnosis of structured VLSI,” IEEE Design and Test of Comp., vol. 6, pp. 49–60, August 1989.

    Google Scholar 

  17. D.J. Burns, “Locating high resistance shorts in CMOS circuits by analyzing supply current measurement vectors,” Int. Symp. for Testing and Failure Analysis, pp. 231–237, 1989.

  18. S. Chakravarty and P.J. Thadikaran, “Simulation and generation of IDDQ tests for bridging and leakage faults,” Tech. Rep. No. 92-16, Dept. of Computer Science, State University of New York, Buffalo, NY 14260.

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Research Partially Supported by NSF Grant No. MIP-9102509.

This work was performed when the author was with the Dept. of Computer Science, State University of New York at Buffalo.

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Chakravarty, S., Liu, M. Algorithms for I DDQ measurement based diagnosis of bridging faults. J Electron Test 3, 377–385 (1992). https://doi.org/10.1007/BF00135341

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