Abstract
In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.
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Jone, WB., Das, S.R. Multiple-output parity bit signature for exhaustive testing. J Electron Test 1, 175–178 (1990). https://doi.org/10.1007/BF00137393
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DOI: https://doi.org/10.1007/BF00137393