Skip to main content
Log in

Optimization-based multifrequency test generation for analog circuits

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Semiconductor Industry Technology Workshop Conclusions, Semiconductor Industry Association, 1993.

  2. L. Milor and V. Visvanathan, “Detection of catastrophic faults in analog integrated circuits,” IEEE Trans. Computer-Aided Design, Vol. 8, pp. 114–130, Feb. 1989.

    Google Scholar 

  3. L. Milor and A. Sangiovanni-Vincentelli, “Optimal Test Set Design for Analog Circuits,” Proc. ICCAD, 1990, pp. 294–297.

  4. L. Milor and A. Sangiovanni-Vincentelli, “Minimizing Production Test Time to Detect Faults in Analog Circuits,” IEEE trans. Computer-Aided Design, Vol. 13, No. 6, pp. 796–813, June 1994.

    Google Scholar 

  5. S.-J. Tsai, “Test Vector Generation for Linear Analog Devices,” Proc. IEEE International Test Conference, 1990, pp. 592–597.

  6. N. Ben Hamida and B. Kaminska, “Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling,” Proc. IEEE International Test Conference, 1993, pp. 652–661.

  7. N. Nagi, A. Chatterjee, A. Balivada, and J. Abraham, “Fault-based Automatic Test Generator for Linear Analog Circuits,” Proc. of ICCAD, 1993, pp. 88–91.

  8. M. Slamani and B. Kaminska, “An Integrated Approach for Analog Circuit Testing with Minimum Number of Detected Parameters,” Proc. IEEE International Test Conference, 1994, pp. 631–649.

  9. G. Devarayanadurg and M. Soma, “Analytical Fault Modeling and Static Test Generation for Analog ICs,” Proc. of ICCAD, 1994, pp. 44–47.

  10. Optimization Toolbox (for use with Matlab) User's Guide, Math-Works, Inc., Dec. 1992.

  11. K. Schittowski, “NLQPL: A Fortran-subroutine Solving Constrained Nonlinear Programming Problems,” Operations Research, Vol. 5, pp. 485–500, 1985.

    Google Scholar 

  12. J.W. Bandler, P.C. Liu, and J.H.K. Chen, “Worst Case Network Tolerance Optimization,” IEEE Trans. Microwave Theory Tech., Vol. MTT-23, pp. 630–641, Aug. 1975.

    Google Scholar 

  13. H. Tromp, “The generalized Tolerance Problem and Worst Case Search,” Proc. IEEE Conf. Computer-Aided-Design of Electronic and Microwave Circuits and Systems, July 1977, pp. 72–77.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Abderrahman, A., Kaminska, B. & Cerny, E. Optimization-based multifrequency test generation for analog circuits. J Electron Test 9, 59–73 (1996). https://doi.org/10.1007/BF00137565

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00137565

Keywords

Navigation