Summary
We consider the design of a ‘tree-multiplier’, which is a modified version of a Wallace tree-multiplier [16] made suitable for VLSI design by Luk and Vuillemin [12]. It is shown that 4 log(n) + 3 test patterns suffice to exhaustively test the multiplier with respect to the ‘cellular fault model’ (which includes tests for all single stuck at faults). Some slight modifications of the multiplier prove, that these tests can be applied without increasing the number of input ports substantially.
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Becker, B. An easily testable optimal-time VLSI-multiplier. Acta Informatica 24, 363–380 (1987). https://doi.org/10.1007/BF00292108
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DOI: https://doi.org/10.1007/BF00292108