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Verification of a multiprocessor cache protocol using simulation relations and higher-order logic

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Abstract

We present a formal verification method for concurrent systems. The technique is to show a correspondence between state machines representing an implementation and specification behavior. The correspondence is called asimulation relation, and is particularly well suited for theorem provers. Since the method does not rely on enumerating all the states, it can be applied to systems with an infinite or unknown number of states. The method is illustrated by proving the correctness of a particularly subtle example that is likely to be of increasing importance: a directory based multiprocessor cache protocol. The proof is carried out using the HOL (higher-order logic) theorem prover.

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Authors and Affiliations

  1. Sun Microsystems Inc., 2550 Garcia Avenue, 94043, Mountain View, CA

    Paul N. Loewesstein

  2. Department of Computer Science, Stanford University, 94305, Stanford, CA

    David L. Dill

Authors
  1. Paul N. Loewesstein
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  2. David L. Dill
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Loewesstein, P.N., Dill, D.L. Verification of a multiprocessor cache protocol using simulation relations and higher-order logic. Form Method Syst Des 1, 355–383 (1992). https://doi.org/10.1007/BF00709156

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