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Cordic based parallel/pipelined architecture for the Hough transform

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Abstract

We present the design of parallel architectures for the computation of the Hough transform based on application-specific CORDIC processors. The design of the circular CORDIC in rotation mode is simplified by the a priori knowledge of the angles participating in the transform and a high throughput is obtained through a pipelined design combined with the use of redundant arithmetic (carry save adders in this paper). Saving area is essential to the design of a pipelined CORDIC and can be achieved through the reduction in the number of microrotations and/or the size of the coefficient ROM. To reduce the number of microrotations we incorporate radix 4, when it is possible, or mixed radix (radix 2 and radix 4) in the design of the processor, achieving a reduction by half and 25% microrotations, respectively, with respect to a totally radix 2 implementation. Furthermore, if we allocate two circular CORDIC rotators into one processors then the size of the shared coefficient ROM is only 50% of the ROM of a design based on two separated rotators. Finally, we have also incorporated additional microrotations in order to reduce the scale factor to one. The result is a pipelined architecture which can be easily integrated in VLSI technology due to its regularity and modularity.

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Authors and Affiliations

  1. Dept. Electrónica, Facultad de Física, Univ. Santiago de Compostela, 15706, Santiago de Compostela, Spain

    J. D. Bruguera

  2. Dept. Arquitectura de Computadores, University of Málaga, Plaza El Ejido, 29013, Málaga, Spain

    N. Guil, J. Villalba & E. L. Zapata

  3. Dept. Elect and Compt. Eng., University of California, 92717, Irvine, CA, USA

    T. Lang

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  1. J. D. Bruguera
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  2. N. Guil
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  3. T. Lang
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  4. J. Villalba
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  5. E. L. Zapata
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Additional information

This work was supported by the Ministry of Education and Science (CICYT) of Spain under project TIC-92-0942.

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Bruguera, J.D., Guil, N., Lang, T. et al. Cordic based parallel/pipelined architecture for the Hough transform. J VLSI Sign Process Syst Sign Image Video Technol 12, 207–221 (1996). https://doi.org/10.1007/BF00924986

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  • DOI: https://doi.org/10.1007/BF00924986

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