Abstract
A multi-stage algorithm is a computing algorithm consisting of a sequence of nested loop constructs to be executed sequentially. In this paper, a systematic approach to address the multi-stage systolic mapping problem is proposed. To reduce the inter-stage data communication overhead, we argue that the adjacent stages should have matched I/O interface. For this, the conditions of I/O matching between two stage's mapping are established. A systematic method to derive the I/O matched mapping is also presented. To improve the performance degradation due to theinitiation andconclusion phases of computation in systolic array, a technique calledchaining which tries to overlap part of the computations in successive stages and thus effectively reduces the computation latency is employed. With these results, the multi-stage mapping problem is formulated as an optimization problem and a heuristic search based multi-stage systolic mapping (MSSM) tool is developed. Several design examples are presented to illustrate the potential use of MSSM.
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Hwang, YT., Hu, Y.H. MSSM—A design aid for multi-stage systolic mapping. J VLSI Sign Process Syst Sign Image Video Technol 4, 125–145 (1992). https://doi.org/10.1007/BF00925118
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DOI: https://doi.org/10.1007/BF00925118