Abstract
This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose newshifted remainder conditioning, andsign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2W–1) to aboutW (whereW is the word-length), when pipelined at the bit-level.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
K.K. Parhi and D.G. Messerschmitt, “Concurrent cellular VLSI adaptive filter architectures,”IEEE Transactions on Circuits and Systems, vol. CAS-34, October 1987, pp. 1141–1151.
K.K. Parhi, “A systematic approach for design of digit serial signal processing architectures,”IEEE Transactions on Circuits and Systems, vol. 38, April 1991, pp. 358–375.
A. Avizienis, “Signed digit number representation for fast parallel arithmetic,”IRE Transactions on Electronic Computers, vol. EC-10, 1961, pp. 389–400.
K. Hwang,Computer Arithmetic: Principles, architecture, and design, NY: Wiley, 1979, pp. 267–360.
A. Vandemeulebroecke, E. Vanzieleghme, T. Denayer, P.G.A. Jespers, “A new carry-free division algorithm and its application to a single-chip 1024-b RSA Processor,”IEEE Journal of Solid-State Circuits, vol. 25, 1990, pp. 748–756.
S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, and N. Takagi, “Design of high speed MOS multiplier and divider using redundant binary representation,” inProc. 8th IEEE Symp. Computer Arithmetic, 1987, pp. 80–86.
M.D. Ercegovac, and T. Lang, “A division algorithm with prediction of quotient digits,”Proc. of 7th IEEE Symp. on Computer Arithmetic, 1985, pp. 51–56.
M.D. Ercegovac, and T. Lang, “Fast Radix-2 division with quotient-digit prediction,”Journal of VLSI Signal Processing, vol. 1, 1989, pp. 169–180; vol. C-36, 1987.
M.D. Ercegovac, T. Lang, and R. Modiri, “Implementation of fast Radix-4 division with operands scaling,”Proc. of the IEEE 9th Symp. on Computer Arithmetic, 1988, pp. 486–489.
M.D. Ercegovac, and T. Lang, “On the fly conversion of redundant into conventional representations,”IEEE Transactions on Computer, vol. C-36, 1987.
E.E. Swartzlander Jr., ed., “Compuer arithemtic,”IEEE Computer Society Press Tutorial, vol. 1 1990.
E.E. Swartzlander, Jr., ed., “Computer arithmetic,”IEEE Computer Aided Society Press Tutorial, vol. 2 1990.
Srinivas H.R., and K.K. Parhi, “High-speed VLSI processor architectures using hybrid number representation,”IEEE, Proceedings of International Conference on Computer Design: VLSI in Computers and Processors, 1991, Cambridge, MA, pp. 564–571.
S.C. Knowles, J.G. McWhirther, R.F. Woods, and J.V. McCanny, “Bit level systolic architectures for high performance IIR filtering,”Journal of VLSI Signal Processing, vol. 1, 1989, pp. 9–24.
M.J. Irwin and R.M. Owens, “Design issues in digit-serial signal processors,” inProc. of IEEE international symposium on circuits and systems, 1989, Portland, Oregon, pp. 441–444.
J.E. Robertson, “A new class of digital division methods,”IRE Trans. on Electronic Computers, 1958, pp. 88–92.
N.H.E. Weste, and K. Eshraghian,Principles of CMOS VLSI Design: A Systems Perspective, Reading, MA: Addison-Wesley, 1988.
LSI Logic Corporation,CMOS Macrocell Manual, 2nd edition, 1985.
T.G. Noll, D.S. Lansiedel, H. Klar, and G. Enders, “A pipelined 330 MHz multiplier,”IEEE Journal of Solid State Circuits, vol. SC-21, 1986, pp. 411–416.
M. Hatamian and G.L. Cash, “A 70-MHz 8-bit×8-bit parallel pipelined multipler in 2.5 μm CMOS,”IEEE Journal of Solid State Circuits, vol. SC-21, 1986, pp. 505–513.
M. Hatamian and G.L. Cash, “Parallel bit-level pipelined VLSI designs for high-speed signal processing,”Proceedings of the IEEE, vol. 75, 1987, pp. 1192–1202.
M.D. Ercegovac and T. Lang, “Fast multiplication without carrypropagate addition,”IEEE Transactions on Computers, vol. 39, 1990.
C.S. Wallace, “A suggestion for a fast multiplier,”IEEE Transactions on Electronic Computers, vol. EC-13, 1964, pp. 14–17.
S.H. Unger, “Tree realizations of iterative circuits,”IEEE Transactions on Computers, vol. C-26, 1977.
Y. Harata, Y. Nakamura, et al., “A high-speed multiplier using redundant binary adder tree,”IEEE Journal of Solid-State Circuits, vol. SC-22, 1987, pp. 28–34.
Author information
Authors and Affiliations
Additional information
This research was supported by the Office of Naval Research under contract number N00014-J-91-1008.
Rights and permissions
About this article
Cite this article
Srinivas, H.R., Parhi, K.K. High-speed VLSI arithmetic processor architectures using hybrid number representation. J VLSI Sign Process Syst Sign Image Video Technol 4, 177–198 (1992). https://doi.org/10.1007/BF00925121
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF00925121