Abstract
We propose a new scheme for the Texas Instruments SN54182/SN74182 lookahead-carry generator. The SN54182/SN74182 provides a redundant carry output,C n+x . Our redesign provides an alternative to the original design that improves the performance of adder implementations. We analyze gate delays of lookahead adders with sizes of 16, 32, and 64 bits. We examine both CMOS-ASIC vendor technology and standard TTL implementations. In all cases, gate delays of sum and carry bits are improved. We also include a layout of our new lookahead-carry generator.
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This is a revised version of a paper that appeared in the Proceedings of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, Vol. 2, pp. 1393–1397, 1994.
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Kwan, H., Nelson, R.L. & Swartzlander, E.E. A new design for a lookahead carry generator. J VLSI Sign Process Syst Sign Image Video Technol 14, 295–302 (1996). https://doi.org/10.1007/BF00929622
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DOI: https://doi.org/10.1007/BF00929622