Skip to main content
Log in

Abstract

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.

We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=ϑ(n 2 T 2 m ) andT=ϑ(T M ) for the parameterT M in\([\log n,\sqrt n ]\) are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. M.A. Soderstrand, W.K. Jenkins, G.A. Jullien, F.J. Taylor, editors,Residue number system arithmetic: Modern applications in digital processing. New York: IEEE Press, 1986.

    MATH  Google Scholar 

  2. W.K. Jenkins and B.J. Leon, “The use of residue number systems in the design of finite impulse response digital filters,”IEEE Trans. Circuits Syst., vol. CAS-24, 1977, pp. 191–201.

    Article  MathSciNet  MATH  Google Scholar 

  3. M.A. Soderstrand, “A high-speed low cost recursive digital filter using residue number arithmetic,”Proc. IEEE, vol. 65, 1977, pp. 1065–1067.

    Article  Google Scholar 

  4. W.K. Jenkins, “Techniques for residue-to-analog conversion for residue-encoded digital filters,”IEEE Trans Circuits Syst., vol. CAS-25, 1978, pp. 555–562.

    Article  Google Scholar 

  5. W.K. Jenkins, “A highly efficient residue-combinatorial architecture for digital filters,”Proc. IEEE, vol. 66, 1978, pp. 700–702.

    Article  Google Scholar 

  6. B.D. Tseng, G.A. Jullien and W.C. Miller, “Implementation of FFT structures using the residue number system,”IEEE Trans. Comput., vol. C-28, 1979, pp. 831–844.

    Article  MATH  Google Scholar 

  7. C.H. Huang, D.G. Peterson, H.E. Rauch, J.W. Teague and D.F. Fraser, “Implementation of a fast digital processor using the residue number system,”IEEE Trans. Circuits Syst., vol. CAS-28, 1981, pp. 32–38.

    Article  Google Scholar 

  8. M.A. Bayoumi, G.A. Jullien and W.C. Miller, “A VLSI model for residue number system architecture,”INTEGRATION, the VLSI journal, vol. 2, 1984, pp. 191–211.

    Article  Google Scholar 

  9. G. Alia, F. Barsi and E. Martinelli, “A fast VLSI conversion between binary and residue systems,”Inform. Process. Lett., vol. 18, 1984, pp. 141–145.

    Article  Google Scholar 

  10. G. Alia and E. Martinelli, “A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system,”IEEE Trans. Circuits Syst., vol. CAS-31, 1984, pp. 1033–1039.

    Article  Google Scholar 

  11. C.D. Thompson, “VLSI design with multiple active layers,”Inform. Process. Lett., vol. 21, 1985, pp. 109–111.

    Article  Google Scholar 

  12. F.J. Taylor, “A VLSI residue arithmetic multiplier,”IEEE Trans. Comput., vol. C-31, 1982, pp. 540–546.

    Article  Google Scholar 

  13. G. Alia, F. Barsi and E. Martinelli, “A fast near optimum VLSI implementation of FFT using residue number systems,”INTEGRATION, the VLSI journal, vol. 2, 1984, pp. 133–147.

    Article  Google Scholar 

  14. G.A. Jullien, “Residue number scaling and other operations using ROM arrays,”IEEE Trans. Comput., vol. C-27, 1978, pp. 325–336.

    Article  MathSciNet  MATH  Google Scholar 

  15. F.J. Taylor, C.H. Huang, “An autoscaler residue multiplier,”IEEE Trans. Comput., vol. C-31, 1982, pp. 321–325.

    Article  Google Scholar 

  16. K. Mehlhorn and F.P. Preparata, “Area-time optimal VLSI integer multiplier with minimum computation time,”Information and Control, vol. 58, 1983, pp. 137–156.

    Article  MathSciNet  MATH  Google Scholar 

  17. C.D. Thompson,A complexity theory for VLSI, Ph.D. Thesis, Carnegie-Mellon University, Computer Science Dept., Aug. 1980.

  18. R.P. Brent and H.T. Kung, “The area-time complexity of binary multiplication,”JACM, vol. 28, 1981, pp. 521–534.

    Article  MathSciNet  MATH  Google Scholar 

  19. C.A. Mead and L.A. Conway,Introduction to VLSI systems, Reading, MA: Addison-Wesley, 1980.

    Google Scholar 

  20. R.P. Brent and H.T. Kung, “A regular layout for parallel adders,”IEEE Trans. Comput., vol. C-31, 1982, pp. 260–264.

    Article  MathSciNet  MATH  Google Scholar 

  21. N.S. Szabo and R.I. Tanaka,Residue arithmetic and its applications to computer technology, New York: McGraw-Hill, 1967.

    MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Additional information

This work has been supported by the National Program on Solid-State Electronics and Devices of the Italian National Research Council.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Alia, G., Martinelli, E. A VLSI structure forX(modm) operation. J VLSI Sign Process Syst Sign Image Video Technol 1, 257–264 (1990). https://doi.org/10.1007/BF00929920

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00929920

Keywords

Navigation