Abstract
High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.
We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=ϑ(n 2 T 2 m ) andT=ϑ(T M ) for the parameterT M in\([\log n,\sqrt n ]\) are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.
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This work has been supported by the National Program on Solid-State Electronics and Devices of the Italian National Research Council.
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Alia, G., Martinelli, E. A VLSI structure forX(modm) operation. J VLSI Sign Process Syst Sign Image Video Technol 1, 257–264 (1990). https://doi.org/10.1007/BF00929920
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DOI: https://doi.org/10.1007/BF00929920