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Bit-Level systolic architectures for high performance IIR filtering

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Abstract

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.

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References

  1. S.C. Knowles, R.F. Woods, J.G. McWhirter, and J.V. McCanny, “Bit-Level Systolic Arrays for IIR Filtering,”Proc IEEE Int Conf on Systolic Arrays, May 1988, pp. 653–663.

  2. J.V. McCanny and J.G. McWhirter, “Some Systolic Array Developments in the UK,”IEEE Computer, vol. 20, no. 7, July 1987, pp. 53–65.

    Article  Google Scholar 

  3. J.V. McCanny and J.G. McWhirter, “Systolic and Wavefront Arrays,”VLSI Technology and Design, eds. J.V. McCanny and J.C. White, Academic Press, 1987, pp. 253–299.

  4. R.F. Lyon, “Filters: An Integrated Digital Filter Subsystem,”VLSI Signal Processing: a Bit-Serial Approach, eds. P.B. Denyer and D. Renshaw, Addison Wesley, 1985, pp. 253–262.

  5. L.B. Jackson, J.F. Kaiser and H.S. McDonald, “An Approach to the Implementation of Digital Filters,”IEEE Trans on Audio and Electroacoustics, vol. AU-16, no. 3, 1968, pp. 413–421.

    Article  Google Scholar 

  6. K.K. Parhi and D.G. Messerschmitt, “Concurrent Cellular VLSI Adaptive Filter Architecures,”IEEE Trans on Circuits and Systems, vol. CAS-34, no. 10, October 1987, pp. 1141–1151.

    Article  Google Scholar 

  7. K.K. Parhi and D.G. Messerschmitt, “Pipelined VLSI Recursive Filter Architecures using Scattered Look-Ahead and Decomposition,”Proc IEEE Int Conf on Acoustics, Speech, and Signal Processing, New York, April 1988, pp. 2120–2123.

  8. H.H. Loomis and B. Sinha, “High Speed Recursive Digital Filter Realization,”Circuits, Systems, and Signal Processing, vol. 3, no. 3, pp. 267–294.

  9. C.W. Wu and P.R. Cappello, “Application Specific CAD of VLSI Second Order Sections,”IEEE Trans on Acoustics, Speech, and Signal Processing, May 1988, pp. 813–825.

  10. K.K. Parhi and D.G. Messerschmitt, “Block Digital Filtering via Incremental Block-State Structure,”Proc IEEE Int Symp on Circuits and Systems, Philadelphia, May 1987, pp. 645–648.

  11. K.K. Parhiet al., “Architecture Considerations for High Speed Recursive Filtering,”Proc IEEE Int Symp on Circuits and Systems, Philadelphia, May 1987, pp. 374–377.

  12. H.T. Kung and M.S. Lam, “Fault-Tolerant VLSI Systolic Arrays and Two-Level Pipelining,”Proc SPIE, vol. 431 (Real Time Signal Processing VI), 1983, pp. 143–158.

    Article  Google Scholar 

  13. A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,”IRE Trans on Electronic Computers, vol. EC-10, Sept. 1961, pp. 389–400.

    Article  MathSciNet  Google Scholar 

  14. M.D. Ercegovac and T. Lang, “On-the-Fly Conversion of Redundant into Conventional Representations,”IEEE Trans on Computers, vol. C-37, no. 7, July 1987, pp. 895–897.

    Article  MathSciNet  Google Scholar 

  15. J. Sklansky, “Conditional-Sum Addition Logic,”IRE Trans on Electronic Computers, vol. EC-9, June 1960, pp. 226–231.

    Article  MathSciNet  Google Scholar 

  16. M.D. Ercegovac, “On-Line Arithmetic: an Overview,”Proc SPIE, vol. 495 (Real Time Signal Processing VII), 1984, pp. 86–93.

    Article  Google Scholar 

  17. R.F. Woods, S.C. Knowles, J.V. McCanny, and J.G. McWhirter, “Systolic IIR Filters with Bit Level Pipelining,”Proc IEEE Int Conf on Acoustics, Speech and Signal Processing, New York, April 1988, pp. 2072–2075.

  18. R.F. Woods, S.C. Knowles, J.G. McWhirter, and J.V. McCanny, “Systolic Building Block for High Performance Recursive Filtering,”Proc IEEE Int Conf on Circuits and Systems. Helsinki, June 1988, pp. 2761–2764.

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Authors and Affiliations

  1. Signal Processing Group, Royal Signals and Radar Establishment, Saint Andrews Road, Great Malvern, Worcestershire, England

    S. C. Knowles & J. G. McWhirter

  2. Department of Electrical and Electronic Engineering, The Queen's University, Stranmillis Road, Belfast, Northern Ireland

    R. F. Woods & J. V. McCanny

Authors
  1. S. C. Knowles
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  2. J. G. McWhirter
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  3. R. F. Woods
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  4. J. V. McCanny
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Knowles, S.C., McWhirter, J.G., Woods, R.F. et al. Bit-Level systolic architectures for high performance IIR filtering. J VLSI Sign Process Syst Sign Image Video Technol 1, 9–24 (1989). https://doi.org/10.1007/BF00932062

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  • DOI: https://doi.org/10.1007/BF00932062

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