Abstract
This paper describes the design of a 16×16 redundant binary multiplier for signed 2's complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.
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This work was supported in part by National Science Foundation grant MIP-9019862.
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Huang, X., Wei, B.W.Y., Chen, H. et al. High-performance VLSI multiplier with a new redundant binary coding. J VLSI Sign Process Syst Sign Image Video Technol 3, 283–291 (1991). https://doi.org/10.1007/BF00936901
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DOI: https://doi.org/10.1007/BF00936901