Abstract
In this article we address the problem of compacting test response data captured in scan paths. We consider linear compactors, e.g., multiple-input signature registers, and the effect of their characteristic polynomials on the number of aliased faults. The novelty of our analysis lies in that it is based on a realistic error model which takes into account the time correlation among the errors in the test response data fed to the compactor. Such a correlation does exist in scan-based compaction, but has not been considered previously. Based on our analysis, we derive three conditions that should be satisfied to minimize aliasing. They impose little restriction on circuit design.
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This work was supported in part by grants from the Natural Sciences and Engineering Research Council of Canada and in part by the British Columbia Advanced Systems Institute.
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Pilarski, S., Ivanov, A. & Kameda, T. On minimizing aliasing in scan-based compaction. J Electron Test 5, 83–90 (1994). https://doi.org/10.1007/BF00971965
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DOI: https://doi.org/10.1007/BF00971965