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Improving quality: Yield versus test coverage

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Abstract

Until now, it has been thought that the best way to improve quality was to improve yield, that is, to improve the manufacturing process so that fewer defective parts are manufactured. This philosophy has been applied to all areas of manufacturing, from widgets to whalers. One of the tenets of this philosophy is that quality should not be tested in, but should be built in via a well-controlled process that is continuously improving. However, when it comes to semiconductors, significant improvements for a process in order to improve yields can cost millions of dollars. In such a capital intensive industry, where the life of a process is only a few years, such investments are often not in the best economic interests of a semiconductor manufacturer. How, then, can the customers' requirements for quality be met? This article shows that for typical values of yield and test coverage, quality improves faster due to improvements in test coverage than it does for improvements in yield. As a result, testing can be used to achieve improvements in quality at lower costs, and therefore more economically, than improvements in the manufacturing process.

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References

  1. T.W. Williams and N.C. Brown, “Defect Level as a Function of Fault Coverage,”IEEE Trans. Comput., vol. C-30, pp. 987–988, Dec. 1981.

    Google Scholar 

  2. D.V. Das, S.C. Seth, P.T. Wagner, J.C. Anderson, V.D. Agrawal, “An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited,”Proc. Int. Test Conf., Washington, DC, pp. 172–720, Sept. 10–14, 1990.

  3. P.C. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang, “The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%?”Proc. Int. Test Conf., Nashville, TN, pp. 358–364, Oct. 26–30, 1991.

  4. V.D. Agrawal, S.C. Seth, and P. Agrawal, “Fault Coverage Requirement in Production Testing of LSI Circuits,”IEEE J. Solid-State Circuits, vol. SC-17, pp. 57–61, Feb. 1982.

    Google Scholar 

  5. J. Galiay, Y. Crouzet, and M. Vergniault, “Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability,”IEEE Trans. Comput., vol. C-29, pp. 527–531, June 1980.

    Google Scholar 

  6. J.P. Shen, W. Maly, and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,”IEEE Design & Test, vol. 2, pp. 13–26, Dec. 1985.

    Google Scholar 

  7. W. Maly, “Realistic Fault Modeling for VLSI Testing,”Proc. 24th DAC, Miami Beach, FL, pp. 173–180, June 28–July 1, 1987.

  8. S.D. Millman,Nonclassical Faults in CMOS Digital Integrated Circuits, Ph.D. thesis, Stanford University, Stanford, CA., Dec. 1989.

    Google Scholar 

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Millman, S.D. Improving quality: Yield versus test coverage. J Electron Test 5, 253–261 (1994). https://doi.org/10.1007/BF00972084

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