Abstract
When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.
Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.
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References
A. Majumdar and S. Sastry, “On the Distribution of Fault Coverage and Test Length in Random Testing of Combinational Circuits,”Proc. of 29th ACM/IEEE Design Automation Conf., pp. 341–346, 1992.
K. Kim, D.S. Ha, and J.G. Tront, “On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self-Testing,”IEEE Trans. on Computer-Aided Design, vol 7, pp. 919–928, Aug. 1988.
M.A. Breuer and A.A. Ismaeel, “Roving Emulation as a Fault Detection Mechanism,”Trans. on Comp., vol. C-35, pp. 933–939, Nov. 1986.
V.D. Agrawal, “Sampling Techniques for Determining Fault Coverage in LSI Circuits,”Joural of Digital Systems, vol. V, pp. 189–202, 1981.
T.W. Williams, “Test Length in a Self-Testing Environment,”IEEE Design & Test, April 1985, vol. 2, pp. 59–63.
W.K. Huang, M. Lightner, and F. Lombardi, “Predicting Fault Coverage for Random Testing of Combinational Circuits,Proc. IEEE Int. Test Conf., pp. 843–848, Sept. 1987.
K.D. Wagner, C.K. Chin, and E.J. McCluskey, “Pseudorandom Testing,”IEEE Trans. on Computers, vol. C-35, pp. 332–343, Mar. 1987.
J. Savir and P.H. Bardell, “On Random Pattern Test Length,”IEEE Trans. on Computers, vol. C-33, pp. 467–474, June 1984.
A. Majumdar,Stochastic Models for Testability Analysis of Digital Circuits, Ph.D. thesis, University of Southern California, Dept. of Electrical Engineering-Systems, 1992.
F.N. David and D.E. Barton,CombinatorialChance, Charles Griffin & Company Limited, London, UK, 1962.
S.K. Jain and V.D. Agrawal, “STAFAN: An Alternative to Fault Simulation,”Proc. 21st Design Automation Conference, pp. 18–23, June 1984.
A. Majumdar and S.B.K. Vrudhula, “Random-Test Length Estimation: Analysis and Techniques,” Tech. Rep. SIUC/DEE/TR-93-2, Dept. of Electrical Engineering, Southern Illinois University at Carbondale, 1993.
S. Jayaraman, “Test Generation for Single Stuck-At Faults in Combinational Circuits Using Binary Decision Diagrams,” Masters Thesis, Dept. of Electrical Engineering, Southern Illinois University-Carbondale, 1993.
R. Krieger, “PLATO: A Tool for Computing Exact Signal Probabilities,”Proc. 6th Int. Conf. on VLSI Design, Bombay, pp. 65–68, Jan. 1993.
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This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.
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Majumdar, A., Vrudhula, S.B.K. Techniques for estimating test length under random test. J Electron Test 5, 285–297 (1994). https://doi.org/10.1007/BF00972088
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DOI: https://doi.org/10.1007/BF00972088