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Tutorial on semiconductor memory testing

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Abstract

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.

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Authors and Affiliations

  1. TRLabs/Department of Electrical Engineering, University of Alberta, T6G 2G7, Edmonton, Alberta, Canada

    B. F. Cockburn

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  1. B. F. Cockburn
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This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP 0105567.

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Cockburn, B.F. Tutorial on semiconductor memory testing. J Electron Test 5, 321–336 (1994). https://doi.org/10.1007/BF00972517

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