Abstract
In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
M. Abramovici, P.R. Menon, and D.T. Miller, “Critical Path Tracing—An Alternative to Fault Simulation,”Proc. of the 20th Design Automation Conf., pp. 214–220, 1983.
K.J. Antreich and M.H. Schultz, “Fast Fault Simulation in Combinational Circuits,”Proc. of Int. Conf. on CAD, pp. 330–333, 1986.
D.B. Armstrong, “A Deductive Method for Simulating Faults in Logic Circuits,”IEEE Trans. Comput. vol C-21, no. 5, pp. 464–471, 1972.
P.H. Bardell, W.H. McAnney, and J. Savir,Built-In Self Test for VLSI: Pseudorandom Techniques, New York: John Wiley & Sons Inc., 1987.
S.Z. Hassan and E.J. McCluskey, “Increased Fault Coverage through Multiple Signatures,”Proc. Fault-Tolerant Computing Symposium-14, June 1984, pp. 354–359.
F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,”Proc. Intl. Symp. on Circuits and Systems, pp. 1929–1934, 1989.
A. Ivanov and V.K. Agarwal, “An Iterative Technique for Calculating Aliasing Probability of Linear Feedback Shift Registers,”Proc. Fault-Tolerant Computing Symposium-18, Tokyo, Japan, June 1988, pp. 70–75.
D. Lambidonis, MEng Thesis, McGill University, “Computation of Exact Fault Coverage for Compact Test Schemes,”-in preparation.
Y.H. Lee and C.M. Krishna, “Optimal Scheduling of Signature Analysis for VLSI testing,”Proc. Int. Test Conf., September 1988.
F. Maamari and J. Rajski, “A Fault Simulation Method Based on Stem Regions,”Proc. Int. Conf. on Computer-Aided Design, November 1988, pp. 170–173.
A. Miczo,Digital Logic Testing and Simulation, John Wiley and Sons, 1986.
S. Seshu, “On an Improved Diagnosis Program,”IEEE Trans. Elect. Comput., vol. EC-12, no. 2, pp. 76–79, 1965.
J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and T. McCarthy, “Statistical Calculation of Fault Detection Probabilities by Fast Fault Simulation,”Proc. Int. Test Conf., pp. 779–784, 1985.
W. Daehn, D. Kannemacher, and J. Castagne, “Vector Length Control for Compiled Code Event Driven Pattern Parallel Fault Simulation,”European Test Conf., pp. 165–170, April 1991.
E. Maamari and J. Rajski, “A Method of Fault Simulation Based on Stem Regions,”IEEE Trans. CAD, vol. 9 no. 2, pp. 212–220, February 1990.
Author information
Authors and Affiliations
Additional information
This work was supported in part by grants from the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Canadian Microelectronics Corporation (CMC) and the British Columbia Advanced Systems Institute (B.C. A.S.I.).
Rights and permissions
About this article
Cite this article
Lambidonis, D., Agarwal, V.K., Ivanov, A. et al. A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes. J Electron Test 6, 75–84 (1995). https://doi.org/10.1007/BF00993131
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00993131