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HIST: A hierarchical self test methodology for chips, boards, and systems

  • Self-test Systems
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Abstract

This article presents the HIST approach, which allows the automated insertion of self test hardware into hierarchically designed circuits and systems to implement the RUNBIST instruction of the IEEE 1149.1 standard. To achieve an optimal and throughout self testable system, the inherent design hierarchy is fully exploited. All chips and boards are provided with appropriate test controllers at each hierarchy level. The approach is able to detect all those faults, which are in the scope of the underlying self test algorithms. In this paper the hierarchical test architecture, the test controllers as well as all necessary synthesis procedures are presented. Finally a successful application of the HIST approach to a cryptography processor is described.

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Authors and Affiliations

  1. Institute for Computer Design and Fault Tolerance, University of Karlsruhe, P. O. Box 6980, 76128, Karlsruhe, Germany

    Oliver F. Haberl & Thomas Kropf

Authors
  1. Oliver F. Haberl
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  2. Thomas Kropf
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Haberl, O.F., Kropf, T. HIST: A hierarchical self test methodology for chips, boards, and systems. J Electron Test 6, 85–106 (1995). https://doi.org/10.1007/BF00993132

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  • DOI: https://doi.org/10.1007/BF00993132

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