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Processor design for portable systems

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Abstract

Processors used in portable systems must provide highly energy-efficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The user-dependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known low-power techniques are re-evaluated against these metrics and in some cases are not found to be appropriate leading to a set of energy-efficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in low-energy, high-performance design.

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References

  1. S. Kunii, “Means of realizing long battery life in portable PCs”,Proceedings of the IEEE Symposium on Low Power Electronics, pp. 12–13, Oct. 1995.

  2. M. Culbert, “Low power hardware for a high performance PDA”,Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, pp. 144–147, March 1994.

  3. T. Ikeda, “ThinkPad low-power evolution”,Proceedings of the IEEE Symposium on Low Power Electronics, pp. 6–7, Oct. 1995.

  4. A. Chandrakasan, A. Burstein, and R.W. Brodersen, “A Low power chipset for portable multimedia applications”,IEEE Journal of Solid State Circuits, Vol. 29, pp. 1415–1428, Dec. 1994.

    Article  Google Scholar 

  5. M. Horowitz, T. Indermaur, and R. Gonzalez, “Low-power digital design”,Proceedings of the IEEE Symposium on Low Power Electronics, pp. 8–11, Oct. 1994.

  6. D. Lidsky and J. Rabaey, “Early power exploration—A world wide web application”,Proceedings of the Thirty-Third Design Automation Conference, June 1996.

  7. T. Burd,Low-Power CMOS Cell Library Design, Methodology, M.S. Thesis, University of California, Berkeley, UCB/ERL M94/89, 1994.

    Google Scholar 

  8. S. Sze,Physics of Semiconductor Devices, Wiley, New York, 1981.

    Google Scholar 

  9. H.J.M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits”,IEEE Journal of Solid-State Circuits, pp. 468–473, Aug. 1984.

  10. R. Muller and T. Kamins,Device Electronics for Integrated Circuits, Wiley, New York, 1986.

    Google Scholar 

  11. A. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-power CMOS digital design”,IEEE Journal of Solid State Circuits, pp. 473–484, April 1992.

  12. Advanced RISC Machines, Ltd.,ARM710 DataSheet, Technical Document, Dec. 1994.

  13. Intel Corp.,Embedded Ultra-Low Power Intel486 TM GX Processor, SmartDieTM Product Specification, Dec. 1995.

  14. A. Stratakos, S. Sanders, and R.W. Brodersen, “A low-voltage CMOS DC-DC converter for portable battery-operated systems”,Proceedings of the Twenty-Fifth IEEE Power Electronics Specialist Conference, pp. 619–626, June 1994.

  15. J. Bunda et al., “16-Bit vs. 32-Bit instructions for pipelined architectures”,Proceedings of the 20th International Symposium on Computer Architecture, pp. 237–246, May 1993.

  16. Advanced RISC Machines, Ltd.,Introduction to Thumb, Developer Technical Document, March 1995.

  17. J. Bunda, W.C. Athas, and D. Fussell, “Evaluating power implications of CMOS microprocessor design decisions”,Proceedings of the International Workshop on Low Power Design, pp. 147–152, April 1994.

  18. P. Freet, “The SH microprocessor: 16-Bit fixed length instruction set provides better power and die size”,Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, pp. 486–488, March 1994.

  19. T. Burd and B. Peters,A Power Analysis of a Microprocessor: A Study of an Implementation of the MIPS R3000 Architecture, ERL Technical Report, University of California, Berkeley, 1994.

    Google Scholar 

  20. J. Montanaro et al., “A 160 MHz 32b 0.5W CMOS RISC microprocessor”Proceedings of the Thirty-Ninth IEEE International Solid-State Circuits Conference—Slide Supplement, pp. 170–171, Feb. 1996.

  21. J. Bunda,Instruction-Processing Optimization Techniques for VLSI Microprocessors, Ph.D. Thesis, The University of Texas at Austin, 1993.

  22. R. Gonzalez and M. Horowitz, “Energy dissipation in general purpose processors”,Proceedings of the IEEE Symposium on Low Power Electronics, pp. 12–13, Oct. 1995.

  23. D. Wall,Limits of Instruction-Level Parallelism, DEC WRL Research Report 93/6, Nov. 1993.

  24. M. Johnson,Superscalar Microprocessor Design, Englewood, Prentice Hall, NJ, 1990.

    Google Scholar 

  25. M. Smith, M. Johnson, and M. Horowitz, “Limits on multiple issue instruction”,Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 290–302, April 1989.

  26. N. Jouppi and D. Wall, “Available instruction-level parallelism for superscalar and superpipelined machines”,Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 272–282, April 1989.

  27. P. Lowney et al., “The multiflow trace scheduling compiler”,The Journal of Supercomputing, Kluwer Academic Publishers, Boston, Vol. 7, pp. 51–142, 1993.

    Google Scholar 

  28. R. Panwar and D. Rennels, “Reducing the frequency of tag compares for low power I-Cache design”,Proceedings of the International Symposium on Low Power Design, pp. 57–62, April 1995.

  29. S. Gary et al., “The powerPC 603 microprocessor: A low-power design for portable applications”,Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, pp. 307–315, March 1994.

  30. V. Tiwari et al., “Instruction level power analysis and optimization of software”,Journal of VLSI Signal Processing, this issue.

  31. A. Chandrakasan,Low Power Digital CMOS Design, Kluwer Academic Publishers, Boston, 1995.

    Book  Google Scholar 

  32. C. Nagendra et al., “A comparison of the power-delay characteristics of CMOS adders”,Proceedings of the International Workshop on Low Power Design, pp. 231–236, April 1994.

  33. T. Callaway and E. Swartzlander, “Optimizing arithmetic elements for signal processing”,VLSI Signal Processing, Vol. 5, IEEE Special Publications, New York, pp. 91–100, 1992.

    Chapter  Google Scholar 

  34. K. Chu and D. Pulfrey, “A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic”,IEEE Journal of Solid State Circuits, pp. 528–532, Aug. 1987.

  35. T. Biggs et al., “A 1 Watt 68040-compatible microprocessor”,Proceedings of the IEEE Symposium on Low Power Electronics, pp. 8–11, Oct. 1994.

  36. J. Lundberg et al., “A 15–150 MHz all-digital phase-locked loop with 50-Cycle lock time for high-performance low-power microprocessors”,Proceedings of the Symposium on VLSI Circuits, pp. 35–36, June 1994.

  37. J. Lorclt,A Complete Picture of the Energy Consumption of a Portable Computer, M.S. Thesis, University of California, Berkeley, 1995.

    Google Scholar 

  38. A. Chandrakasan, M. Srivastava, and R.W. Brodersen, “Energy efficient programmable computation”,Proceedings of the Seventh International Conference on VLSI Design, pp. 261–264, Jan. 1994.

  39. Intel Corp. and Microsoft Corp.,Advanced Power Management (APM): BIOS Interface Specification, Technical Document, Feb. 1996.

  40. M. Wieser et al., “Scheduling for reduced CPU energy”,Proceedings of the First USENIX Symposium on Operating Systems Design and Implementation, pp. 13–23, Nov. 1994.

  41. K. Govil, E. Chan, and H. Wasserman, “Comparing algorithms for dynamic speed-setting of a low-power CPU”,Proceddings First ACM International Conference on Mobile Computing and Networking, pp. 13–25, Nov. 1995.

  42. Integrated Device Technology, Inc.,Enhanced Orion 64-Bit RISC Microprocessor, Data Sheet, Sept. 1995.

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Authors and Affiliations

  1. Department of EECS, University of California at Berkeley, Berkeley, USA

    Thomas D. Burd & Robert W. Brodersen

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  1. Thomas D. Burd
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  2. Robert W. Brodersen
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Burd, T.D., Brodersen, R.W. Processor design for portable systems. J VLSI Sign Process Syst Sign Image Video Technol 13, 203–221 (1996). https://doi.org/10.1007/BF01130406

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