Abstract
Image segmentation is a crucial part of machine vision applications. In this paper a system to perform real-time segmentation of images is presented. It uses a real-time segmentation VLSI chip that is based on a gradient relaxation algorithm and is designed using the Path Programmable Logic design methodology developed at the University of Utah. The system design considerations, system specifications, and an input/output format for the chip are discussed. The actual design of the chip is given that uses pipeline methodology to achieve real-time performance with a compact VLSI layout. The implementation of the segmentation system is presented and the segmentation chip and the overall system are evaluated with regard to real-time performance and segmentation results.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Anderson RL (1985) Real-time gray-scale video processing using a moment-generating chip. IEEE Journal of Robotics and Automation, RA-1(2)(June):79–85
Barbe DF (1981) VHSIC systems and technology. IEEE Computer, 14(2):13–22
Bhanu B (1986) Automatic target recognition: State of the art survey. IEEE Transactions on Aerospace and Electronic Systems, AES-22(4)(July):364–379
Bhanu B, Faugeras OD (1982) Segmentation of images having unimodal distributions. IEEE Transactions on Pattern Analysis and Machine Intelligence, PAMI-4(4)(July):408–419
Bhanu B, Faugeras OD (1984) Shape matching of two-dimensional objects. IEEE Transactions on Pattern Analysis and Machine Intelligence, PAMI-6(2)(March):137–156
Bhanu B, Holben RD (1990) Model based segmentation of FLIR images. IEEE Transactions on Aerospace & Electronic Systems, AES-26(1)(January)
Bhanu B, Parvin BA (1987) Segmentation of natural scenes. Pattern Recognition, 20(5):487–496
Fouse SD, Cumming AD, Wong VS, Nudd GR (1981) Development of VLSI image understanding systems. Technical Report 1050, USC Image Processing Institute, Los Angeles, California (September), 111–128
Fu KS (Ed.) (1984) VLSI for pattern recognition and image processing. Springer-Verlag
Kruger RP, Thompson WB (1981) A technic al and economic assessment of computer vision for industrial inspection and robotic assembly. Proceedings of IEEE 69:1524–1538
Kung HT, Foster MJ (1980) Design of special-purpose VLSI chips: Example and opinions. IEEE Computer, 13(1)(January):26–40
Mead C, Conway L (1980) Introduction to VLSI systems. Addison-Wesley Publishing Company, Reading, MA
Nagin P, Hanson A, Riseman E (1982) Studies in global and local histogram guided relaxation algorithms. IEEE Transactions on Pattern Analysis and Machine Intelligence. PAMI-4(3)(May):263–277
Nudd GR, Nygaard PA, Fouse SD, and Nussmeier TA (1979) Development of custom designed integrated circuits for image understanding. Technical Report USCIPI 910, USC Image Processing Institute, Los Angeles, California, 120–145
Offen RJ (1985) VLSI image processing. McGraw-Hill Book Company, New York
Ohlander R, Price K, Reddy DR (1978) Picture segmentation using a recursive region splitting method. Computer Graphics and Image Processing 8:313–333
Rosenfeld A, Hummel R, Zucker S (1976) Scene labeling by relaxation operations. IEEE Transactions on Systems, Man and Cybernetics SMC-6(6)(June):420–433
Smith KF (1983) Design of regular arrays using CMOS in PPL. Proceedings of IEEE International Conference on Computer Design/VLSI in Computers, 1–4
Smith KF, Carter TM, Hunt CE (1982) Structured logic design of integrated circuits using the storage/logic array (SLA). IEEE Transactions on Electron Devices 4(April):765–776
Smith KF, Israelson P (1985) Comparison of the Path Programmable Logic design methodology with other custom and semicustom approaches. IEEE International Conference on Computer Design/VLSI in Computers, (October):73–76
Weste NHE, Eshraghian K (1985) Principles of CMOS VLSI design, a system perspective. Addison-Wesley Publishing Company, Reading, MA
Willet TJ (1978) Hardware implementation of image processing using overlays: Relaxation. Proceedings DARPA Image Understanding Workshop, 175–181
Author information
Authors and Affiliations
Additional information
This work was supported in part by Grant ISI-856-0393 from the National Science Foundation.
Rights and permissions
About this article
Cite this article
Bhanu, B., Hutchings, B.L. & Smith, K.F. VLSI design and implementation of a real-time image segmentation processor. Machine Vis. Apps. 3, 21–44 (1990). https://doi.org/10.1007/BF01211450
Issue Date:
DOI: https://doi.org/10.1007/BF01211450