Abstract
A processor with three concurrent and data-shared execution units is described in detail in this paper. The functionality, resources, and data sizes of the execution units, implemented with Xilinx FPGA chips, are user-configurable in order to best fit the application being run. A Harvard-type architecture allows a very large instruction word (128 bits) and, therefore, a real parallel utilization and control of resources. We also present the results of the implementation of two applications, the game of Life and the Abingdon Cross benchmark.
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Iseli, C., Sanchez, E. Spyder: A SURE (SUperscalar and REconfigurable) processor. J Supercomput 9, 231–252 (1995). https://doi.org/10.1007/BF01212870
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DOI: https://doi.org/10.1007/BF01212870