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A scalable, real-time, image processing pipeline

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Abstract

To speed up image processing in the field of robot vision and industrial inspection, a pipeline element that can perform fast cellular logic operations was made. This cellular logic processing element (CLPE) can process binary images with a speed of 100ns per pixel. The processing element is a CMOS VLSI device. It includes a writable logic array for storing sets of 3 × 3 structuring elements that define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed gray-value processing and cellular logic processing.

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Authors and Affiliations

  1. Pattern Recognition Section, Faculty of Applied Physics, Delft University of Technology, P.O. Box 5046, NL-2600, GA Delft, The Netherlands

    Pieter P. Jonker, Erwin R. Komen & Martin A. Kraaijveld

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  1. Pieter P. Jonker
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  2. Erwin R. Komen
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  3. Martin A. Kraaijveld
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Correspondence to Pieter P. Jonker.

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Jonker, P.P., Komen, E.R. & Kraaijveld, M.A. A scalable, real-time, image processing pipeline. Machine Vis. Apps. 8, 110–121 (1995). https://doi.org/10.1007/BF01213476

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