Abstract
A denotational semantics and a Hoare programming logic for a subset of the standard hardware description languageVHDL are set out here. Both define the behaviour of synchronously clockedVHDL simulators in declarative and compositional style. The logic is proved complete with respect to the denotational semantics and a natural implementation of the logic inPROLOG as a validation condition generator forVHDL is also described.
The subset of the language referred to above essentially consists of elaboratedVHDL excluding only deltadelayed signal assignments and zero waits. However, for brevity, only one of the two forms ofVHDL signal assignment is treated here. Moreover, for simplicity, signal resolution functions and local state are assumed to have been encoded away via expressions and signals.
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Breuer, P.T., Fernández, L.S. & Kloos, C.D. A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL. Form Method Syst Des 7, 27–51 (1995). https://doi.org/10.1007/BF01383872
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DOI: https://doi.org/10.1007/BF01383872