Abstract
In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
A. V. Aho, J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison Wesley, Reading, MA, 1974.
W. R. Heller, G. Sorkin, and K. Maling, The Planar Package for System Designers,Proc. 19th ACM/IEEE Design Automation Conf. (1982), pp. 253–260.
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing,Science,220 (1983), 671–680.
U. Lauther, A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation,Journal of Digital Systems,IV (1) (1980), 21–34.
D. P. LaPotin and S. W. Director, Mason: A Global Floor-Planning Tool,Proc. Intl. Conf. on Computer-Aided Design (1985), pp. 143–145.
K. Maling, S. H. Mueller, and W. R. Heller, On Finding Most Optimal Rectangular Package Plans,Proc. 19th ACM/IEEE Design Automation Conf. (1982), pp. 663–670.
R. H. J. M. Otten and L. P. P. P. van Ginneken, Floorplan Design using Simulated Annealing,Proc. Intl. Conf. on Computer-Aided Design (1984), pp. 96–98.
R. H. J. M. Otten, Automatic Floorplan Design,Proc. 19th ACM/IEEE Design Automation Conf. (1982), pp. 261–267.
R. H. J. M. Otten, Efficient Floorplan Optimization,Proc. Intl. Conf. on Computer Design (1983), pp. 499–502.
B. Preas and C. S. Chow, Placement and Routing Algorithms for Topological Integrated Circuit Layout,Proc. Intl. Symp. on Circuits and Systems (1985), pp. 17–20.
B. Preas and W. M. VanCleemput, Placement Algorithms for Arbitrary Shaped Blocks,Proc. 16th ACM/IEEE Design Automation Conf. (1979), pp. 474–480.
L. Sha and R. W. Dutton, An Analytical Algorithm for Placement of Arbitrary Sized Rectangular Blocks,Proc. 22nd ACM/IEEE Design Automation Conf. (1985), pp. 602–608.
C. Sechen and A. Sangiovanni-Vincentelli, The Timberwolf Placement and Routing Package,IEEE Journal of Solid-State Circuits,20 (2) (1985), 510–522.
L. Stockmeyer, Optimal Orientations of Cells in Slicing Floorplan Designs,Information and Control,59 (1983), 91–101.
D. F. Wong and C. L. Liu, A New Algorithm for Floorplan Design,Proc. 23rd ACM/IEEE Design Automation Conf. (1986), pp. 101–107.
D. F. Wong, Algorithmic Aspects of VLSI Circuit Layout, Ph.D. Thesis, University of Illinois at Urbana-Champaign, January, 1987.
L. S. Woo, C. K. Wong, and D. T. Tang, Pioneer: A Macro-Based Floor-Planning Design System,VLSI Systems Design (1986), pp. 32–43.
Author information
Authors and Affiliations
Additional information
Communicated by C. K. Wong.
This work was partially supported by the Semiconductor Research Corporation under Contract 86-12-109, by the National Science Foundation under Grant MIP 8703273, and by a grant from the General Electric Company.
Rights and permissions
About this article
Cite this article
Wong, D.F., Liu, C.L. Floorplan design of VLSI circuits. Algorithmica 4, 263–291 (1989). https://doi.org/10.1007/BF01553890
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF01553890