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A video-rate JPEG chip set

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Abstract

A two-chip set has been designed, fabricated and is fully functional which performs the baseline JPEG image compression and decompression algorithm. The major functions of the devices include: DCT and IDCT, forward and inverse quantization, Huffman coding and decoding. The devices operate with pixel rates beyond 30 MHz at 70 degrees C and 4.75 V. Each die is less than 10 mm on a side and was implemented in a 1.0 µ CMOS cell-based technology to achieve a 9 man-month design time.

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Authors and Affiliations

  1. DSP Division, LSI Logic Corporation, 1525 McCarthy Blvd., 95035, Milpitas, CA

    Peter A. Ruetz, Po Tong, Daniel Luthi & Peng H. Ang

Authors
  1. Peter A. Ruetz
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  2. Po Tong
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  3. Daniel Luthi
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  4. Peng H. Ang
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Ruetz, P.A., Tong, P., Luthi, D. et al. A video-rate JPEG chip set. J VLSI Sign Process Syst Sign Image Video Technol 5, 141–150 (1993). https://doi.org/10.1007/BF01581291

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  • DOI: https://doi.org/10.1007/BF01581291

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