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Architectural strategies for high-throughput applications

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Abstract

In this article an architecture is presented which allows efficient ASIC implementations of high throughput applications. Examples of these applications can be found in real time video applications such as EDTV, IDTV and HDTV. A key issue in the architecture is to provide a balance between memory resources and processing resources. Special attention is paid to the communication between these two types of resources. Architectural techniques are proposed to solve bottlenecks in the memory bandwidth and conflicts between memory accesses. Architectures for address generation in combination with location assignment are presented. The flexibility of the architectural model allows an efficient hardware realization on an ASIC exploiting the inherent parallelism of a particular application. This is illustrated in the article using a complex video algorithm for Progressive Scan Conversion. The proposed architecture is used as a target architecture which drives the high-level synthesis approach of the PHIDEO compiler.

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Authors and Affiliations

  1. Philips Research Labs, P.O. Box 80.000, 5600 JA, Eindhoven, The Netherlands

    J. van Meerbergen, P. Lippens, B. Mcsweeney, W. Verhaegh, A. van der Werf & A. van Zanten

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  1. J. van Meerbergen
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  2. P. Lippens
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  3. B. Mcsweeney
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  4. W. Verhaegh
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  5. A. van der Werf
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  6. A. van Zanten
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van Meerbergen, J., Lippens, P., Mcsweeney, B. et al. Architectural strategies for high-throughput applications. J VLSI Sign Process Syst Sign Image Video Technol 5, 201–220 (1993). https://doi.org/10.1007/BF01581296

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  • DOI: https://doi.org/10.1007/BF01581296

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