Skip to main content
SpringerLink
Log in

A mixed-signal VLSI competitive neuroprocessor for video motion detection

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

VLSI design of a competitive neural network for video motion detection is presented. Massively parallel neurocomputing is performed by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is carried out by using an analog point-to-point interconnection scheme, while global data communication between the host computer and neuroprocessors is achieved through a digital common bus. Experimental results of the analog circuit blocks and system-level analysis on a sequence of real-world images are also presented.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. K. Pazdny, “On the information in optical flows,”Computer Vision, Graphics and Image Processing, vol. 22, 1983, pp. 239–259.

    Article  Google Scholar 

  2. J. Hutchinson, C. Koch, J. Luo, and C. Mead, “Computing motion using analog and binary resistive networks,”IEEE Computer Magazine, 1988, pp. 52–63.

  3. B. Horn and B. Schunck, “Determining optical flow,”Artificial Intelligence, vol. 17, 1981, pp. 185–203.

    Article  Google Scholar 

  4. Y. Zhou and R. Chellappa, “Computation of optical flow using a neural network,”Proc. of IEEE Int. Conf. on Neural Networks, vol. 2, 1988, pp. 71–78.

    Article  Google Scholar 

  5. Y.-T. Zhou, R. Chellappa, “A network for motion perception,”Proc. of IEEE/INNS International Joint Conference on Neural Networks, vol. II, 1990, pp. 875–884.

    Google Scholar 

  6. S. Ullman,The Interpretation of Visual Motion, Cambridge, MA: M.I.T. Prss, 1979.

    Google Scholar 

  7. T. Morishita, Y. Tamura, and T. Otsuki, “A BiCMOS analog neural network with dynamically updated weights, ”Technical Digest of IEEE International Solid-State Circuits Conference, 1990, pp. 142–143.

  8. B.W. Lee and B.J. Sheu, “A compact and general-purpose neural chip with electrically programmable synapses,”IEEE Custom Integrated Circuits Conference Proceedings, 1990, pp. 26.6.1–26.6.4.

  9. C. Toumazou, F.J. Lidgey, and D.G. Haigh, (Eds),Analog IC Design: The Current-Mode Approach, England, IEE/Peter Peregrinus, 1990.

    Google Scholar 

  10. R. Gregorian and G.C. Temes,Analog MOS Integrated Circuits for Signal Processing, New York: John Wiley, 1986.

    Google Scholar 

  11. P.W. Hollis and J.J. Paulos, “Artificial neural networks using MOS analog multipliers,”IEEE J. Solid-State Circuits, vol. 25, 1990, p. 849–855.

    Article  Google Scholar 

  12. S. Satyanarayana, Y.P. Tsividis, and H.P. Graf, “A reconfigurable VLSI neural network,”IEEE J. Solid-State Circuits, vol. 27, 1992, pp. 67–81.

    Article  Google Scholar 

  13. B.J. Sheu, J. Choi, W.-C. Fang, and C.-F Chang, “An analog neural network processor for self-organizing mapping,”Technical Digest of IEEE International Solid-State Circuits Conference, 1992, pp. 136–137, 266.

  14. J. van der Spiegel, P. Muller, D. Blackman, P. Chance, C. Donham, R. Etienne, and P. Kinget, “An analog neural computer with modular architecture for real-time dynamic computations, ”IEEE J. Solid-State Circuits, vol. 27, 1992, pp. 82–92.

    Article  Google Scholar 

  15. B.E. Boser and E. Sackinger, “An analog neural network processor with programmable network topology,”Technical Digest of IEEE International Solid-State Circuits Conference, 1991, pp. 184–185.

  16. N.I. Khachab and M. Ismail, “A nonlinear CMOS analog cell for VLSI signal and information processing,”IEEE J. Solid-State Circuits, vol. 26, 1991, pp. 1689–1699.

    Article  Google Scholar 

  17. J. Lazzaro, S. Ryckebush, M.A. Mahowald, and C.A. Mead, “Winner-take-all network of O(N) complexity,”Advances in Neural Information Processing Systems—I, pp. 703–711, San Mateo, CA: Morgan Kauffman, 1989.

    Google Scholar 

  18. A.G. Andreou et al., “Current-mode subthreshold MOS circuits for analog VLSI neural systems,”IEEE Trans. on Neural Networks, vol. 2, 1991, pp. 205–213.

    Article  Google Scholar 

  19. B.W. Lee and B.J. Sheu,Hardware Annealing in Analog VLSI Neurocomputing, Boston: Kluwer Academic, 1991.

    Book  MATH  Google Scholar 

  20. R. Hecht-Nielsen,Neurocomputing, Reading, MA: Addison-Wesley, 1990, pp. 64–70.

    Google Scholar 

  21. J. Choi and B.J. Sheu, “Analog VLSI neural network imnplementations of hardware annealing and winner-take-all functions,”Proc. of 34th Midwest Symposium on Circuits and Systems, 1991.

  22. P. Allen and D. Holberg,CMOS Analog Circuit Design, New York: Holt, Rinehart, and Winston, 1987.

    Google Scholar 

  23. C. Tomovich, “MOSIS—A gateway to silicon,”IEEE Circuits and Devices Magazine, vol. 4, 1988, pp. 22–23.

    Article  Google Scholar 

  24. G. Lewicki, “Foresight: A fast turn-around and low cost ASIC prototyping alternative,”Proc. of IEEE ASIC Seminar and Exhibit, p. 6–8.1/8.2, 1990.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering— Electrophysics and Systems, the Signal and Image Processing Institute, University of Southern California, 90089-0271, Los Angeles, CA

    Ji-chien Lee, Bing J. Sheu & Rama Chellappa

Authors
  1. Ji-chien Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bing J. Sheu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Rama Chellappa
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

This research was partially supported by National Science foundation under Grant MIP-8904172 and by TRW Inc.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lee, Jc., Sheu, B.J. & Chellappa, R. A mixed-signal VLSI competitive neuroprocessor for video motion detection. J VLSI Sign Process Syst Sign Image Video Technol 6, 57–66 (1993). https://doi.org/10.1007/BF01581959

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01581959

Keywords

Search

Navigation