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Optimal mapping in direct mapped cache environments

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Abstract

In this paper we study positioning strategies for improving the performance of a memory system with a direct mapped cache. A positioning technique determines for every program item, (instruction or data), its address in main memory.

Assuming the Independent Reference Model, we break the general positioning problem into two, the collision minimization and the grouping problems and show optimal algorithms for both problems. Using these algorithms we derive an optimal algorithm for the general positioning problem.

Since the optimal positioning is of very special structure we consider other, less restricted, positionings. We show that the quality of a class of natural assignments that distribute the items almost arbitrarily is good as long as the optimal hit ratio is sufficiently large. Another possible requirement is that the items should be distributed as evenly as possible. We find an optimal assignment for the special case of the pair assignment.

In addition we look at the expected performance gain of two frequently suggested cache features. The cache bypass feature supports the access of items in memory without loading the item into the cache. We show an assignment with best possible hit ratio. Also it is shown that a cache which employs a random assignment policy, i.e., the assignment of an item is determined randomly, does not improve the expected hit ratio.

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References

  1. A. Agarwal, P. Chow, M. Horowitz, J. Acken, A. Saltz and J. Hennessy, “On chip caches for high performance processors,” in P. Losleben, ed.,Proceedings of the Conference on Advanced Research in VLSI, Stanford University, Stanford, CA, and University of California, Berkeley, CA (1987) pp. 1–24.

    Google Scholar 

  2. S. Anily and A. Federgruen, “Structured partitioning problems,”Operations Research 39(1) (1991) 130–149.

    Google Scholar 

  3. A.K. Chakravarty, J.B. Orlin and U.G. Rothblum, “Consecutive optimizers for a partitioning problem with applications to optimal inventory groupings for joint replenishment,”Operations Research 33(4) (1985) 820–834.

    Google Scholar 

  4. P.A. Franaszek and T.J. Wagner, “Some distribution free aspects of paging algorithm performance,”Journal of the ACM 21(1) (1974) 31–39.

    Google Scholar 

  5. R. Gupta and C.-H. Chi, “Improving instruction cache behavior by reducing cache pollution,” in:Proceedings Supercomputing 90 (1990) pp. 82–91.

    Google Scholar 

  6. D.J. Hartfield and J. Gerald, “Program restructuring for virtual memory,”IBM Systems Journal 10(3) (1971) 168–192.

    Google Scholar 

  7. S.J. Hartly, “Compile-time program restructuring in multiprogrammed virtual memory systems,”IEEE Transactions on Software Engineering 14(11) (1988) 1640–1644.

    Google Scholar 

  8. M.D. Hill, “Aspects of cache memory and instruction buffer performance,” PhD thesis, University of California (Berkeley, CA, 1987).

    Google Scholar 

  9. Y. Hollander and A. Itai, “On the complexity of direct caching,” TR 794, Computer Science Department, Technion (Haifa, Israel, 1993).

    Google Scholar 

  10. W.-M.W. Hwu and P.P. Chang, “Achieving high instruction cache performance with an optimizing compiler,” in:Proceedings of the 16th Symposium on Computer Architecture, Jerusalem, Israel (1989) pp. 242–250.

  11. R. Karp, “Reducibility among combinatorial problems,” in: R. Miller and G. Thatcher, ed.,Complexity of Computer Computations. (Plenum, New York, 1972).

    Google Scholar 

  12. D.E. Knuth, “An analysis of optimum caching,”Journal of Algorithms, 6 (1985) 181–199.

    Google Scholar 

  13. S. McFarling, “Program optimization for instruction caches,” in:Third International Conference on Architectural Support for Programming Languages and Operating Systems (1989) pp. 183–191.

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Gal, S., Hollander, Y. & Itai, A. Optimal mapping in direct mapped cache environments. Mathematical Programming 63, 371–387 (1994). https://doi.org/10.1007/BF01582076

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  • DOI: https://doi.org/10.1007/BF01582076

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