Configurable array logic circuits for computing network error detection codes

Abstract

Configurable Array Logic (CAL) has a basic architecture which is a cellular array with nearest neighbor connections. The cells in the array are dynamically programmable using transistor switches controlled by static RAM cells. Each cell can realize any two-input Boolean operation or act as a simple latch, as well as providing routing for pass-through connections to allow non-neighbor inter-cell connections. In this article, we demonstrate the versatility of the CAL technology by presenting efficient CAL circuits for computing all of the major error detection codes now in use for worldwide computer networking; these include CCITT, IEEE, Internet and ISO standard codes. The circuits, each having a version which comfortably fits on to a single 32×32 cell CAL chip, are appropriate for use as hardware accelerators to help computers deal with the ever increasing rates of data transmission over networks. The first class of error detection codes described are thecyclic redundancy codes (CRCs), which are in virtually universal use for bit serial transmission over physical links. The other class of error detection codes described are themodulo 2ⁿ — 1checksums, which are in common use for byte transmission over networks and inter-networks.