Abstract
Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
White, S.A., “Applications of distributed arithmetic to digital signal processing: a tutorial review,”IEEE ASSP Magazine, 1989.
Elliott, D.F. ed., “Handbook of digital signal processing,” Reading, MA: Academic Press, 1987, pp. 964–972.
Peled, A. and Liu, B., “Digital signal processing,” New York: John Wiley, 1976, Chap. 5, pp. 212–260.
Xilinx Inc., “The Programmable Gate Array Data Book,” 1992.
Zoran Corp., “ZR33881 Digital Filter Processor Data Sheet.
Harris Semiconductor Corp., “HSP43881 Digital Filter Data Sheet.”
AT&T Corporation, “DSP-16 Data Sheet.”
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Mintzer, L. FIR filters with field-programmable gate arrays. J VLSI Sign Process Syst Sign Image Video Technol 6, 119–127 (1993). https://doi.org/10.1007/BF01607876
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF01607876