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A superfast algorithm for single-error correction in rrns and hardware implementation

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Abstract

The modular algebraic structure of the residue number systems (RNS) leads to modularity and parallelism in the hardware implementation for the RNS-based arithmetic processor [1], [2]. Both modularity and parallelism are essential to fully utilize the very-large-scale integrated (VLSI) technology [3]. In this work, a superfast algorithm for correcting single residue errors in the RNS is developed with a slight increase in redundancy. Based on this algorithm and another recently proposed fast algorithm, two architectures are designed for their hardware implementation. The hardware complexity for this superfast algorithm isO(k) while the hardware complexity for previously known algorithms isO(k 2). The performance of this new technique is compared to the previously known techniques in terms of computational speed and other criteria.

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, Syracuse University, 13244-1240, Syracuse, N.Y.

    J. -D. Sun, H. Krishna & K. -Y. Lin

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  1. J. -D. Sun
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  2. H. Krishna
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  3. K. -Y. Lin
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Sun, J.D., Krishna, H. & Lin, K.Y. A superfast algorithm for single-error correction in rrns and hardware implementation. J VLSI Sign Process Syst Sign Image Video Technol 6, 259–269 (1993). https://doi.org/10.1007/BF01608538

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  • DOI: https://doi.org/10.1007/BF01608538

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