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Abstract

Synchronous dataflow (SDF) has been used to synthesize code for programmable DSPs to implement multirate and block oriented signal processing systems. However, with large block sizes, or significant sample rate changes, program memory consumption becomes a critical problem. This article develops a compile-time algorithm for scheduling SDF graphs to exploit opportunities for looping—the successive reoccurrence of identical firing patterns. Because SDF graphs allow actors to produce or consume an arbitrary number of tokens on each input or output, complicated control flow may result. Yet in static scheduling, it is desirable to execute sections of the target code within loop constructs, such as “do-while,” to reduce program-memory requirements. To do this, the SDF graph is hierarchically clustered, carefully avoiding deadlock while exposing looping opportunities. Results of applying these loop-extraction algorithms show orders of magnitude of compaction for target program code space on programmable DSPs compared to in-line code.

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References

  1. E.A. Lee and David G. Messerschmitt, “Synchronous dataflow,” Proceedings of the IEEE, September 1987.

  2. E.A. Lee, W.-H. Ho, E. Goei, J. Bier, and S.S. Bhattacharyya, “Gabriel: a design environment for DSP,”IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37(11), 1989, pp. 1751–1762.

    Article  Google Scholar 

  3. H. Printz,Automatic Mapping of Large Signal Processing Systems to a Parallel Machine, Memorandum CMU-CS-91-101, School of Computer Science, Carnegie Mellon University, May 15, 1991. PhD Thesis.

  4. P.N. Hilfinger,Silage References Manual, Draft Release 2.0, Computer Science Division, EECS Dept., University of California at Berkeley, July 8, 1989.

  5. J.B. Dennis, “First version of a dataflow procedure language,”MIT/LCS/TM-61. Laboratory for Computer Science, MIT, 545 Technology Square, Cambridge, MA 02139.

  6. E.A. Lee, “Programmable DSP architectures: part I,”IEEE ASSP Magazine, vol. 5(4), October, 1988, pp. 4–19.

    Article  Google Scholar 

  7. E.A. Lee, “Programmable DSP architectures: part II,”IEEE ASSP Magazine, vol. 6(1), January, 1989, pp. 4–14.

    Article  Google Scholar 

  8. S. How, “Code Generation for Multirate DSP Systems in GABRIEL,” Master's Degree Report, U.C. Berkeley, May, 1990.

  9. W.-H. Ho, Edward A. Lee, and D.G. Messerschmitt, “High level dataflow programming for digital signal processing,”VLSI Signal Processing III, IEEE Press, 1988.

  10. W.-H. Ho, “Code Generation for Digital Signal Processors Using Synchronous Dataflow,” Master's Degree Report, U.C. Berkeley, May, 1988.

  11. S.S. Bhattacharyya, “Clustering Formalism For Synchronous Dataflow,” Technical Report UCB/ERL M92/30, U.C. Berkeley, Berkeley, CA 94720, April, 1992.

    Google Scholar 

  12. E.A. Lee and D.G. Messerschmitt, “ Static scheduling of synchronous dataflow programs for digital signal processing,”IEEE Transactions on Computers vol. C-36(2), 1987, pp. 24–35.

    Article  Google Scholar 

  13. S. Ha, J. Buck, E.A. Lee, and D.G. Messerschmitt, “PTOLEMY: A Platform for Heterogeneous Simulation and Prototyping,” European Simulation Conference, June, 1991.

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Bhattacharyya, S.S., Lee, E.A. Scheduling synchronous dataflow graphs for efficient looping. J VLSI Sign Process Syst Sign Image Video Technol 6, 271–288 (1993). https://doi.org/10.1007/BF01608539

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  • DOI: https://doi.org/10.1007/BF01608539

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