Abstract
The complexity of adding twon-bit numbers on a two-dimensional systolic array is investigated. We consider different constraints on the systolic array, including:
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whether or not the input and output ports lie on the periphery of the array,
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constraints placed on the arrival and departure times of inputs and outputs
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For all combinations of the above constraints, we obtain optimal tradeoffs among the resources of area, pipeline delay, and worst-case time. It turns out that there is a subtle interplay among the constraints and some of our results seem counterintuitive. For instance, we show that allowing more-significant bits to arrive earlier than less-significant bits can speed up addition by a factor of logn. We also show that multiplexing can often result in a smaller array. On the other hand, we show that some known results, such as Chazelle and Monier's bounds for arrays that have input/output ports on the perimeter, also hold in less constrained models.
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Communicated by F. Thomson Leighton.
The research of S. Rao Kosaraju was supported by NSF Grant No. MCS 8506361.
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Aggarwal, A., Carter, J.L. & Kosaraju, S.R. Optimal tradeoffs for addition on systolic arrays. Algorithmica 6, 49–71 (1991). https://doi.org/10.1007/BF01759034
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DOI: https://doi.org/10.1007/BF01759034