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Global wire routing in two-dimensional arrays

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Abstract

We examine the problem of routing wires of a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case “channel-width” needed to route ann×n array, and develop provably good heuristics for the general case. Single-turn routings are proved to be near-optimal in the worst-case.

A central result of our paper is a “rounding algorithm” for obtaining integral approximations to solutions of linear equations. Given a matrix A and a real vector x, then we can find an integral x such that for alli, ¦x i -x i ¦ <1 and (Ax) i -(Ax) i <Δ. Our error bound Δ is defined in terms of sign-segregated column sums of A:

$$\Delta = \mathop {\max }\limits_j \left( {\max \left\{ {\sum\limits_{i:a_{ij} > 0} {a_{ij} ,} \sum\limits_{i:a_{ij}< 0} { - a_{ij} } } \right\}} \right).$$

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Communicated by C. K. Wong.

This research was supported by funds from NSF Grant DCR-84-11954 (Karp), ARPA N00014-80-C-0622 (Leighton), AFOSR 82-0326 (Leighton), NSF Presidential Young Investigator Award with matching funds from Xerox and IBM (Leighton), NSF Grant MCS-80-06938 (Rivest), Semiconductor Research Corporation Grant 82-11-008 (Thompson), NSF Grant MCS 82-04506 (U. V. Vazirani), NSF Grant BCR 85-03611 (U. V. Vazirani), and an IBM Graduate Fellowship (V. V. Vazirani).

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Karp, R.M., Leighton, F.T., Rivest, R.L. et al. Global wire routing in two-dimensional arrays. Algorithmica 2, 113–129 (1987). https://doi.org/10.1007/BF01840353

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  • DOI: https://doi.org/10.1007/BF01840353

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