Abstract
An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved.
The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester.
The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders.
High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988.
LSI, L64240 Multi-bit Filter (MFIR), Technical report, LSI Logic Corporation, Headquarters, Milpitas, CA, 1989.
Plessey, PDSP16488 Single Chip Convolver with Integral Line Delays, Technical report, Plessey Semiconductors Ltd., Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom, 1988.
W. Kamp, R. Künemund, H. Söldner, and R. Hofer, “Programmable 2D linear filter for video applications,”IEEE Journal of Solid State Circuits, 1990, pp. 735–740.
M. Chean and J.A.B. Fortes, “A taxonomy of reconfiguration techniques for fault-tolerant processor arrays,”Computer, 1990, pp. 55–69.
F. Lombardi and D. Sciuto, “A compared evaluation of classes of reconfiguration strategies for fault tolerance in VLSI array processor architectures,” In (J. McCanny, J. McWhirter, and E. Swartzlander Jr., eds.),Systolic Array Processors. Englewood Cliffs, NJ: Prentice Hall, 1989.
V. Hecht, K. Rönner, and P. Pirsch, “A defect tolerant systolic array implementation for real time image processing,” InProc. 1991 Application Specific Array Processors, Barcelona, Spain, 1991, IEEE Computer Society Press, pp. 25–39.
V. Hecht, “Hardward supplements in bit-serial systolic arrays for processing of border-pixels in 2-dimensional image transformations,” InProc. IFIP Workshop on Parallel Architectures on Silicon, Grenoble, France, 1989, pp. 399–412.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Hecht, V., Rönner, K. & Pirsch, P. A defect-tolerant systolic array implementation for real time image processing. J VLSI Sign Process Syst Sign Image Video Technol 5, 37–47 (1993). https://doi.org/10.1007/BF01880270
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF01880270