Abstract
Ahomotopic routability problem asks whether a VLSI layout can be made legal by applying continuous deformations (homotopies) to its wires. This paper presents an optimally efficient algorithm for deciding homotopic routability under polygonal and grid-based wiring rules. The algorithm runs in timeO(N logN) and spaceO(N), whereN is the number of line segments composing the input.
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Communicated by A. S. LaPaugh.
This research was supported in part by a Mathematical Sciences Postdoctoral Research Fellowship from the National Science Foundation, Grant DMS-8705835.
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Maley, F.M. Testing homotopic routability under polygonal wiring rules. Algorithmica 15, 1–16 (1996). https://doi.org/10.1007/BF01942604
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DOI: https://doi.org/10.1007/BF01942604