Abstract
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.
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Dean, M.E., Dill, D.L. & Horowitz, M. Self-timed logic using Current-Sensing Completion Detection (CSCD). Journal of VLSI Signal Processing 7, 7–16 (1994). https://doi.org/10.1007/BF02108186
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DOI: https://doi.org/10.1007/BF02108186