Summary
In this paper we propose a novel way of deriving a family of fully-pipelined linear systolic algorithms for the computation of the solutions of a dynamic programming problem. In many instances, modularity is an important feature of these algorithms. One may simply add more processors to the array as the size of the problem increases. Each cell has a fixed amount of local storage α and the time delay between two consecutive cells of the array is constant. The time complexity and the number of cells in our array tend ton 2+O(n) andn 2/α +O(n), respectively, as α increases. This represents the best known performance for such an algorithm.
Similar content being viewed by others
References
Benaini A, Tchuente M: Matrix product on linear systolic Arrays. In: Cosnard M, Quinton P, Raynal M, Robert Y (eds) Parallel and distributed algorithms. North Holland 1989
Benaini A, Robert Y: A modular systolic linear array for Gaussian Elimination. Int J Comput Math 36:105–118 (1990)
Chen MC: A design methodology for synthesizing parallel algorithms and architectures. J Parallel Distrib Comput 3:461–491 (1986)
Delosme JM, Ispen ICF: An illustration of a methodology for the construction of efficient systolic architectures. VLSI Int Symp on VLSI Technology, Systems and Applications. Taipei Taiwan 1985, pp 268–273
Fisher AL, Kung HT: Synchronizing large VLSI processor arrays. Proc Tenth Ann IEEE/ACM Symp Comput Architec 1983 pp 54–58
Gachet P, Joinnault B, Quinton P: Synthesizing systolic arrays using DIASTOL. Proc 1rst Intern Workshop on Systolic Arrays. Oxford 1986 pp 25–36
Guibas LJ, Kung HT, Thompson CD: Direct VLSI implementation of combinatorial algorithms. Proc Conf very Large Scale Integration: Architecture, Design, Fabrication. California Institute of Technology 1979 pp 509–525
Huang CH, Langauer C: An incremental mechanical development of systolic solutions to the algebraic path problem. Acta Inf 27:97–124 (1989)
Hwang K, Cheng YH: Partitioned matrix algorithms for VLSI arithmetic systems. IEEE Trans Comput C-31, 1215–1224 (1982)
Knuth DE: The art of computer programming, vol 3: Sorting and searching, Addison-Wesley 1973
Kung HT: Why systolic architectures? IEEE Compt 15:37–46 (1980)
Kung SY, Lo SC: A spiral systolic architecture algorithm for transitive closure problems. Proc IEEE Int Conf Comput Design 1985
Lee P, Kedem Z: Synthesizing linear array algorithms from nested for loop algorithms. IEEE Trans Comput C-37:1578–1598 (1988)
Leighton FT, Leiserson, CE: Wafer scale integration of systolic arrays. Proc Twenty-third Symp Found Comput Sci 1982, pp 297–311
Lisper B: Synthesis of synchronous systems by static scheduling in space-time. Lect Notes Comput Sci vol 362. Springer Berlin Heidelberg New York 1989
Lisper B: Computing transitive closure on systolic arrays of fixed size. Distrib Comput 5:133–144 (1991)
Louka B, Tchuente M: Dynamic programming on two-dimensional systolic arrays. Inform Process Lett 29:97–104 (1988)
Moldovan DI, Fortes JA: Partitioning and mapping algorithms into fixed size systolic arrays. IEEE Trans Comput C-35:1–12 (1986)
Myoupo JF: Dynamic programming on linear pipelines. Inform Process Lett 39:333–341 (1991)
Myoupo JF: A fully-pipelined solutions constructor for dynamic programming problems. In: Advances in computing-ICCI'91. Proc Inter Conf Comput Inform Ottawa 1991. Lect Notes Comput Sci, vol 497. Springer, Berlin Heidelberg New York 1991
Myoupo JF: Solving dynamic programming problems efficiently on modular linear pipeline. Proc 11th Annual IEEE Int Phenonix Conf Computers and Communications, Scottdate, Arizona 1992
Myoupo JF: A way of deriving linear systolic arrays from a mathematical algorithm description: case of the Warshall-Floyd algorithm. Proc Int Conf Parall Process ICPP 1:575–579 (1991)
Myoupo JF: Synthesizing linear systolic arrays for dynamic programming problems. Parallel Process Lett 2(1):97–110 (1992)
Prasanna Kumar VK, Tsai VC: Designing linear systolic arrays. J Parallel Distr Comput 7(3):441–463 (1989)
Prasanna Kumar VK, Tsai YC: Mapping dynamic programming onto a linear systolic array. J. VLSI Signal Process 1(4):335–344 (1990)
Rajopadhye S: Synthesizing systolic arrays with control signals from recurrence equations. Distrib Comput 3:88–105 (1989)
Ramakrishnan IV, Fussel DS, Silberschatz A: Mapping homogenous graphs on linear arrays. IEEE Trans Comput C-35 (3):189–209 (1986)
Ramakrishnan IV, Varman PJ: Dynamic programming and transitive closure on linear pipelines. Proc. Int Conf Parallel Process 1984, pp 359–364
Ramakrishnan IV, Varman PJ: Synthesis of an optimal family of matrix multiplication algorithms on linear arrays. IEEE Trans Comput C-35 (11) 989–996 (1986)
Van Scoy FL: The parallel recognition of classes of graphs. IEEE-TC C-29, (7):563–570 (1980)
Xue J, Lengauer C: On one-dimensional systolic arrays. Proc ACM Int Worshop on Formal Methods in VLSI design. Springer Berlin Heidelberg New York 1991
Xue J, Lengauer C: Specifying, control signals for one-dimensional systolic arrays by uniform recurrence equations. In: Quinton P, Robert Y (eds) Algorithms and parallel VLSI architectures II. Elsevier 1991
Author information
Authors and Affiliations
Additional information
Jean Frédéric Myoupo received his B.Sc in mathematics from the University of Yaounde, Cameroon, in 1980, and the M.S. and Ph.D. degrees both in applied mathematics from the Université Paul Sabatier de Toulouse, France in 1981 and 1983 respectively. From 1983 to 1985, he was lecturer at the Université de Sherbrooke, Québec, Canada. From 1985 to 1990, he was Assistant-Professor at the University of Yaounde, Cameroon. Since October 1990, he has been Associate-Professor in the department d'Informatique and Laboratoire de Recherche en Informatique (L.R.I.) of the Université de Paris-Sud, France. His current research interests include design of systolic algorithms and architectures, parallel and distributed processing.
Rights and permissions
About this article
Cite this article
Myoupo, J.F. Mapping dynamic programming onto modular linear systolic arrays. Distrib Comput 6, 165–179 (1993). https://doi.org/10.1007/BF02242705
Received:
Accepted:
Issue Date:
DOI: https://doi.org/10.1007/BF02242705