Abstract
Two discrete optimization problems arising in VLSI are to reduce the area of a programmable logic array (PLA) and to separate graphs uniformly. We show that a commonly used area reduction technique called blockfolding is equivalent to separating graphs by vertex deletion. The later problem is shown to be NP-complete even for 3-regular-graphs.
Zusammenfassung
Zwei diskrete Optimierungsprobleme beim VLSI-Design sind die Fläche eines programmierbaren logischen Arrays (PLA) zu reduzieren und einen Graphen in möglichst gleich große Teilgraphen zu zerlegen. Wir zeigen, daß eine in der Praxis oft benutzte Flächenreduktionstechnik, das Blockfolding, äquivalent ist zu dem Problem, Graphen durch Wegnahme von Knoten zu zerlegen. Es wird gezeigt, daß dieses Problem schon für 3-reguläre GraphenNP-schwer ist.
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Müller, R., Wagner, D. α-Vertex separator is NP-hard even for 3-regular graphs. Computing 46, 343–353 (1991). https://doi.org/10.1007/BF02257778
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DOI: https://doi.org/10.1007/BF02257778