Skip to main content
SpringerLink
Log in

PHIDEO: High-level synthesis for high throughput applications

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

This paper describes a new approach to high-level synthesis for high throughput applications. Such applications are typically found in real-time video systems such as HDTV. The method is capable of dealing with hierarchical flow graphs containing loops with manifest boundaries and linear index expressions. The algorithm is based on the model of periodic operations which allows optimizations across loop boundaries. Processing units and storage units are minimized simultaneously. The algorithm is implemented in thePHIDEO system. The major parts of this system are the processing unit synthesis, the scheduler and the memory synthesis including address generation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. J.L. van Meerbergen, P.E.R. Lippens, B. McSweeney, W.F.J. Verhaegh, A. van der Werf, and A. van Zanten, “Architectural Strategies For High-Throughput Applications,”Journal of VLSI Signal Processing, Vol. 5, pp. 201–220, 1993.

    Article  Google Scholar 

  2. D.J. Mallon and P.B. Denyer, “A New Approach To Pipeline Optimisation,”Proceedings of the EDAC, Glasgow, March 1990, pp. 83–88.

  3. P.N. Hilfinger, “A high-level language and silicon compiler for digital signal processing,”Proceedings of the Custom Integrated Circuits Conference, May 1985.

  4. M.C. McFarland, A. Parker and R. Camposano, “The High-Level Synthesis of Digital Systems,”Proceedings of the IEEE, 1990, pp. 301–318.

  5. R.K. Brayton, R. Camposano, G. DeMicheli, R. Otten and J. van Eijndhoven, “The Yorktown Silicon Compiler” in D. D. Gajski, Ed.Silicon Compilation, Reading, MA:Addison-Wesley, 1988, pp. 204–311.

    Google Scholar 

  6. F.D. Brewer and D.D. Gajski, “Knowledge Based Control in Micro-Architecture Design,”Proceedings of the 24th Design Automation Conference, New York, NY:ACM/IEEE, June 1987, pp. 203–209.

    Google Scholar 

  7. P. Marwedel, “A new synthesis algorithm for the MIMOLA software system,”Proceedings of the 23rd Design Automation Conference, New York, NY:ACM/IEEE, June 1986, pp. 271–277.

    Google Scholar 

  8. P.G. Paulin, J.P. Knight and E.F. Girczyc, “HAL: A Multi-Paradigm Approach to Automatic Datapath Synthesis,”Proceedings of the 23rd Design Automation Conference, New York, NY:ACM/IEEE, June 1986, pp. 263–270.

    Google Scholar 

  9. L. Stok and R. van den Born, “EASY: Multiprocessor Architecture optimization,”Proc. of the Int. Workshop on Logic and Architecture Synthesis for Silicon Compilers, Grenoble, May 25–27 1988, pp. 1–15.

  10. D. E. Thomas, E. M. Dirkes, R. A. Walker, J. V. Rajan, J.A. Nestor, and R.L. Blackburn, “The System Architect's Workbench,” inProceedings of the 25th Design Automation Conference, New York, NY:ACM/IEEE, June 1988, pp. 337–343.

    Google Scholar 

  11. H. Trickey “Flamel: A High-Level Hardware Compiler,”IEEE Transactions on CAD, Vol. CAD-6, 1987, pp. 259–269.

    Article  Google Scholar 

  12. A.H.M. van Roermund, P.J. Snijder, H. Dijkstra, C.G. Hemeryck, C. M. Huizer, J.M.P. Schmitz and R.J. Sluijter, “A General-Purpose Programmable Video Signal Processor,”IEEE Transactions on Consumer Electronics, Vol. 35, 1989, pp. 249–258.

    Article  Google Scholar 

  13. A.E. Casavant, M.A. D'Abreu, M. Dragomirecky, D.A. Duff, J.R. Jasica, M. J. Hartman, K. S. Hwang and W. D. Smith, “A Synthesis Environment for Designing DSP Systems,”IEEE Design and Test of Computers, 1989, pp. 35–44.

  14. H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. van Meerbergen and J. Huisken, “Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms,Proceedings of the IEEE, 1990, pp. 319–335.

  15. B. Haroun and M. Elmasry, “SPAID: An Architectural Synthesis Tool for DSP Custom Applications,”IEEE Journal of Solid State Circuits, Vol. 24, 1989, pp. 426–435.

    Article  Google Scholar 

  16. J. Schuck, M. Glesner and M. Lacken, “First results and design experience with silicon Compiler ALGIC,”VLSI Signal processing II, New York, IEEE Press, 1986.

    Google Scholar 

  17. R. Woudsma, F. Beenker, J. van Meerbergen and C. Niessen, “Piramid: an architecture-driven silicon compiler for complex DSP applications,”Proceedings IEEE International Symposium on Circuits and Systems, 1990, pp. 2696–2700.

  18. M. Potkonjak and J. Rabaey, “A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs,”Proc. of the Design Automation Conference, June 1989, pp. 7–12.

  19. J. Rabaey and M. Potkonjak, “Resource Driven Synthesis in the HYPER System,”Proc. of the ISCAS, New Orleans, May, 1990, pp. 2592–2595.

  20. P. Lippens, J. van Meerbergen, A. van der Werf, W. Verhaegh, B. McSweeney, J. Huisken and O. McArdle, “Phideo: a silicon compiler for high speed algorithms,”Proceedings European Conference on Design Automation, Amsterdam (Netherlands), February 1991, pp. 436–441.

  21. Th. Krol, J. van Meerbergen, C. Niessen, Smits W. and J. Huisken, “The SPRITE Input Language: An intermediate format for High Level Synthesis,”Proceedings of the European Design Automation Conference (EDAC), Brussels, Belgium, March 1992, pp. 186–192.

  22. C.E. Leiserson, F.M. Rose and J.B. Saxe, “Optimizing Synchronous Circuitry by Retiming,”Third Caltech Conference on Very Large Scale Integration, 1983.

  23. A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens and W. Verhaegh, “Hierarchical retiming including pipelining,”Proceedings International Conference on VLSI (VLSI-91), Glasgow (U.K.), August 1991, pp. 11.2.1–11.2.10.

  24. S. Note, F. Catthoor, G. Goossens and H. De Man, “Combined hardware selection and pipelining in high-performance data-path design,”Proceedings of the International Conference on Computer Design, Port Chester, NY, Oct. 1990, pp. 328–331.

  25. A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens and W. Verhaegh, “Flexible Datapath Compilation for Phideo,”Proceedings of the Euro ASIC Conference, Paris, May 1991, pp. 178–183.

  26. C.B. Shung, R. Jain, K. Rimey, E. Wang, M.B. Srivastava, B. C. Richards, E. Lettang, S.K. Azim, L. Thon, P.N. Hilfinger, J.M. Rabaey and R. W. Broderson, “An Integrated CAD System for Algorithm-Specific IC Design,”IEEE Transactions on CAD, Vol. 10, 1991, pp. 447–482.

    Article  Google Scholar 

  27. A. van der Werf, E.H.L. Aarts, M.J.A. Peek, J.L. van Meerbergen, P.E.R. Lippens and W.F.J. Verhaegh, “Area Optimization of Multi-Functional Processing Units,” ICCAD, Santa Clara, Nov. 1992.

    Google Scholar 

  28. W. Verhaegh, E. Aarts, J. Korst and P. Lippens, “Improved force-directed scheduling,”Proceedings European Design Automation Conference, Amsterdam (Netherlands), February 1991, pp. 430–435.

  29. P.G. Paulin and J.P. Knight, “Force-Directed Scheduling for the Behavioral Synthesis of ASICs,”IEEE Transactions on CAD, Vol. 8, 1989.

  30. P. Lippens, J. van Meerbergen, A. van der Werf, W. Verhaegh and B. McSweeney, “Memory synthesis for high speed DSP applications,”Proceedings IEEE Custom Integrated Circuits Conference, (CICC-91), San Diego (Calif., U.S.A.), May 1991, pp. 11.7.1–11.7.4.

  31. M. Balakrishnan et al., “Allocation of Multiport Memories in Data Path Synthesis,”IEEE Trans. on CAD, Vol. 7, 1987, pp 536–40.

    Article  Google Scholar 

  32. Chien-In Henry Chen and G.E. Sobelman, “Single-port/Multiport Memory Synthesis in Data Path Design,”Proceedings of the ISCAS, New Orleans, Louisiana, USA, May 1–3 1990, pp. 1110–1113.

  33. L. Stok, “Interconnect Optimisation during Data Path Allocation,”Proc. of the European Design Automation Conference, Glasgow, March 1990, pp. 141–145.

  34. J.L. van Meerbergen, P.E.R. Lippens, W.F.J. Verhaegh and A. van der Werf, “Relative Location Assignment for Repetitive Schedules,” Proceedings of the European Conference on Design Automation with the European Event in ASIC Design, Paris, 1993, pp. 403–407.

  35. D.M. Grant, P.B. Denyer and I. Finlay, “Synthesis of Address generators,”Proceedings of the IEEE Conference on Computer Aided Design, Santa Clara, CA, Nov. 1989, pp. 116–119.

  36. D.M. Grant and P.B. Denyer, “Address Generation for Array Access Based on Modulus m Counters,”Proceedings European Conference on Design Automation, Amsterdam 1991, pp. 118–122.

  37. F. Beenker et al., “A testability strategy for silicon-compilers,” Proc. International Test Conference, pp. 660–669, Washington DC, August 1989.

Download references

Author information

Authors and Affiliations

  1. Philips Research Laboratories, Eindhoven, The Netherlands

    J. L. Van Meerbergen, P. E. R. Lippens, W. F. J. Verhaegh & A. Van Der Werf

Authors
  1. J. L. Van Meerbergen
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. P. E. R. Lippens
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. W. F. J. Verhaegh
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. A. Van Der Werf
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Van Meerbergen, J.L., Lippens, P.E.R., Verhaegh, W.F.J. et al. PHIDEO: High-level synthesis for high throughput applications. Journal of VLSI Signal Processing 9, 89–104 (1995). https://doi.org/10.1007/BF02406472

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02406472

Keywords

Search

Navigation