Skip to main content
SpringerLink
Log in

Optimization of VLIW compatibility systems employing dynamic rescheduling

  • Published:
International Journal of Parallel Programming Aims and scope Submit manuscript

Abstract

Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a general-purpose computing paradigm. Previous approaches include hardware and software techniques, both of which have drawbacks. Hardware techniques add to the complexity of the architecture, whereas software techniques require multiple executables. This paper presents a technique called Dynamic Rescheduling that applies software techniques dynamically, using intervention by the OS: at each first-time page fault, the page of code is rescheduled for the new generation, if required. Results are presented to demonstrate the viability of the technique using the Illinois IMPACT compiler and the TINKER architectural framework. For the machine models and the workloads used in this study, performance of the rescheduled code compares well with the native scheduled code for a machine. The behavior of a subset of programs in the workload is such that they face a large number of first-time page faults. Due to this, their rescheduling overhead is higher relative to their total execution time. Such programs are calledhigh-overhead programs. Caching of translated pages across multiple invocations of the program to reduce the rescheduling overhead, using apersistent rescheduled-page cache (PRC) (1) is discussed. It was found that for the workload used in this evaluation, a PRC of size between 512 to 1024 pages, and which uses anoverhead-based page replacement policy would be effective in reducing the overhead.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. T. M. Conte, S. W. Sathaye, and S. Banerjia, A Persistent Rescheduled Page Cache for Low-Overhead Object-Code Compatibility in VLIW Architectures, inProc. 29th Ann. Int’l. Symp. on Microarchitecture, Paris, France (December 1996).

  2. J. S. O’Donnell, Superscalar vs. VLIW,Computer Architecture News (ACM SIGARCH), pp. 26–28 (March, 1995).

  3. B. R. Rau, Dynamically scheduled VLIW processors,Proc. 26th. Ann Int’l. Symp. on Microarchitecture, Austin, Texas, pp. 80–90 (December 1993).

  4. S. Melvin, M. Shebanow, and Y. Patt, Hardware Support for Large Atomic Units in Dynamically Scheduled Machines,Proc. 21th Ann. Int’l. Symp. on Microarchitecture, San Diego, California, pp 60–66 (December 1988).

  5. M. Franklin and M. Smotherman, A Fill-Unit Approach to Multiple Instruction Issue,Proc. 27th Ann. Int’l. Symp. on Microarchitecture, San Jose, California, pp. 162–171 (December 1994).

  6. T. M. Conte and S. W. Sathaye, Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures,Proc. 28th Ann. Int’l. Symp. on Microarchitecture, Ann Arbor, Michigan (November 1995).

  7. G. Silberman and K. Ebcioğlu, An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures,Computer,26:39–56 (June 1993).

    Article  Google Scholar 

  8. R. L. Sites, A. Chernoff, M. B. Kirk, M. P. Marks, and S. G. Robinson, Binary Translation,Comm. ACM,36:69–81 (February 1993).

    Article  Google Scholar 

  9. J. Turley, Alpha Runsx86 Code with fx!32,Microprocessor Report, Vol. 10 (March 1996).

  10. P. Koch, Emulating the 68040 in the PowerPC, Macintosh,Proc. Microprocessor Forum, (October 1994).

  11. P. Stears, Emulating thex86 and DOS/Windows in RISC Environments,Proc. Microprocessor Forum (October 1994).

  12. R. Cmelik and D. Keppel, SHADE: A fast Instruction-Set Simulator for Execution Profiling, inFast Simulation of Computer Architectures, T. M. Conte and C. E. Gimarc, (eds.), Kluwer Academic Publishers, Boston, Massachusetts, (1994).

    Google Scholar 

  13. M. S. Schlansker and V. K. Kathail, Techniques for Critical Path Reduction of Scalar Programs, Tech. Report HPL-95-112, Hewlett-Packard Laboratories, Palo Alto, California, (1995).

  14. W. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery, The Superblock: An Effective structure for VLIW and Superscalar Compilation,The Journal of Supercomputing,7:229–248 (January 1993).

    Article  Google Scholar 

  15. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann, Effective Compiler Support for Predicated Execution using the Hyperblock,Proc. 25th Ann. Int’l. Symp. on Microarchitecture, Portland, Oregon, pp. 45–54 (December 1992).

  16. TINKER machine language manual, 1995; Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, 27695-7911.

  17. V. Kathail, M. Schlansker, and B. R. Rau, HPL PlayDoh Architecture Specification: version 1.0, Technical Report HPL-93-80 Hewlett-Packard Laboratories, Technical Publications Department, 1501 Page Mill Road, Palo Alto, California (February 1994).

  18. T. M. Conte, S. Banerjia, S. Y. Larin, K. N. Menezes, and S. W. Sathaye, Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings,Proc. 29th An. Int’l Symp. on Microarchitecture, Paris, France (December 1996).

  19. T. M. Conte,Systematic Computer Architecture Prototyping. Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, Illinois, (1992).

    Google Scholar 

  20. B. R. Rau, Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops,Proc. 27th Ann. Int’l Symp. on Microarchitecture, San Jose, California, (November 1994).

  21. B. R. Rau, Iterative Modulo Scheduling, Technical Report HPL-94-115, Hewlett-Packard Laboratories, Technical Publications Department, 1501 Page Mill Road, Palo Alto, California, (1995).

  22. J. R. Ellis,Bulldog: A Compiler for VLIW Architectures. Cambridge, Massachusetts, The MIT Press, (1986).

    Google Scholar 

  23. P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Warter, and W. W. Hwu, IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors,Proc. 18th Ann. Int’l. Symp. Computer Architecture, Toronto, Canada, pp. 266–275 (May 1991).

  24. Hewlett Packard, How HP-UX Works: Concepts for the System Administrator (R9.0). Palo Alto, California, Hewlett Packard, (1991).

  25. Data General, Programming in the DG/UX Kernel Environment (R4.11). Westboro, Massachussets, Data General (1995).

  26. G. Kane,MIPS RISC Architecture. Englewood Cliffs, New Jersey, Prentice-Hall (1992).

    Google Scholar 

  27. S. Weiss and J. E. Smith,POWER and PowerPC. San Francisco, California, Morgan Kaufmann (1994).

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695-7911, North, Carolina

    Thomas M. Conte & Sumedh W. Sathaye

Authors
  1. Thomas M. Conte
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sumedh W. Sathaye
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

This is a revised and expanded version of the paper presented by the authors at the28th Annual International Symposium on Microarchitecture (MICRO-28), November 1995, Ann Arbor, Michigan.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Conte, T.M., Sathaye, S.W. Optimization of VLIW compatibility systems employing dynamic rescheduling. Int J Parallel Prog 25, 83–112 (1997). https://doi.org/10.1007/BF02700048

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02700048

Key Words

Search

Navigation