Abstract
A novel parallel delayed least-mean-square (PDLMS) algorithm is proposed by introducing the parallel processing method into delayed LMS (DLMS) algorithm. Compared with DLMS, the algorithm presented has the property of smaller delay, higher throughput rate and faster convergence speed, while it also exhibits some de-correlation effect for the correlated input sequence. These properties make it more suitable for the cases of high order filter with high convergence speed. At the same time, it can be mapped onto the high-speed and/or high-pipelined hardware structure directly.
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Jaggi, S., Martinez, A. B., Upper and lower bounds of the misadjustment in the LMS algorithm, IEEE Trans. on Acoustics, Speech, and Signal Processing, 1990, 38(1): 164–166.
Rupp, M., Frenzel, R., Analysis of LMS and NLMS algorithms with delayed coefficient update under the presence of spherically invariant processes, IEEE Trans. on Signal Processing, 1994, 42(3): 668–672.
Guo, L., Ljung, L., Exponential stability of general tracking algorithms, IEEE Trans. on Automatic Control, 1995, 40(8): 1376–1387.
Guo, L., Ljung, L., Performance analysis of general tracking algorithms, IEEE Trans. on Automatic Control, 1995, 40(8): 1388–1402.
Bershad, N. J., Behavior of the ɛ-normalized LMS algorithm with gaussian inputs, IEEE Trans. Acoustics, Speech, and Signal Processing, 1987, 35(5): 636–644.
Eweda, E., Transient performance degradation of the LMS, RLS, sign, signed regressor, and sign-sign algorithms with data correlation, IEEE Trans, on Circuits and Systems-II, Analog and Digital Signal Processing, 1999, 46(8): 1055–1063.
Goel, M., Shangbhag, N. R., Finite-precision analysis of the pipelined strength-reduced adaptive filter, IEEE Trans. on Signal Processing, 1998, 46(6): 1763–1769.
Thomas, J., Pipelined systolic architectures for DLMS adaptive filtering, Journal of VLSI Signal Processing, 1996, 12: 223–246.
Douglas, S. C., Zhu, Q., Smith, K. F., A pipelined LMS adaptive FIR filter architecture without adaptation delay, IEEE Trans. on Signal Processing, 1998, 46(3): 775–779.
Shanbhag, N. R., Goel, M., Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN, IEEE Trans. on Signal Processing, 1997, 45(5): 1276–1290.
Ramanatan, S., Visvanathan, V., Nandy, S. K., Architectural synthesis of computational engines for subband adaptive filtering, Journal of VLSI Signal Processing, 1999, 22(3): 173–195.
Zhu, Q., Douglas, S. C., Smith, K. F., A pipelined architecture for LMS adaptive FIR filter without adaptation delay, ICASSP’97, Munich, Germany, 1997, 1933–1936.
Matsubara, K., Nishikawa, K., Kiya, H., A new pipelined architecture of the LMS algorithm without degradation of convergence characteristics, ICASSP’97, Munich, Germany, 1997, 4125–4128.
Matsubara, K., Nishikawa, K., Kiya, H., Pipelined LMS adaptive filter using a new look-ahead transformation, IEEE Trans. on Circuits and Systems-II, Analog and Digital Signal Processing, 1999, 46(1): 51–55.
Hu, G. R., Hou, C. H., Sun, Y. G., A VLSI-oriented RLS adaptive filter algorithm and implementation, Acta Electranica Sinica, 1996, 24(8): 76–82.
Meyer, M. D., P.agrawall, D., A high sampling rate delayed LMS filter architecture, IEEE Trans. on Circuits and Systems-II, Analog and Digital Signal Processing, 1993, 40(11): 727–729.
Herzberg, H., Cohen, R. H., Be’ery, Y., A systolic array realization of an LMS adaptive filter and the effects of delayed adaptation, IEEE Trans. on Signal Processing, 1992, 40(11): 2799–2803.
Long, G. Z., Ling, F. Y., Proakis, J. G., The LMS algorithm with delayed coefficient adaptation, IEEE Trans. on Signal Processing, 1989, 37(9): 1397–1405.
Long, G. Z., Ling, F. Y., Proakis, J. G., Corrections to ‘the LMS algorithm with delayed coefficient adaptation’, IEEE Trans. on Signal Processing, 1992, 40(1): 230–232.
Shanbhag, N. R., Parhi, K. K., Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM coder, IEEE Trans. on Circuits and Systems-II, Analog and Digital Signal Processing, 1993, 40(12): 753–766.
Parker, D. A., Parhi, K. K., Low-area/power parallel FIR digital filter implementations, Journal of VLSI Signal Processing, 1997, 17: 75–92.
Fiore, P. D., Low-complexity implementation of a polyphase filter bank, Digital Signal Processing, 1998, 8: 126–135.
Berberidis, K., Theodoridis, S., A new fast block adaptive algorithm, IEEE Trans. on Signal Processing, 1999, 47(1): 75–87.
Shang, Y., Wu, S. J., Design of parallel adaptive FIR filters, IEEE APCCAS’98, Chiangmai, Thailand, IEEE, 1998, 81–84.
Shang, Y., Wu, S. J., Systolic structure of the adaptive FIR filter based on polynomial decomposition, Journal of Electronics China, 2000, 22(5): 768–774.
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Shang, Y., Wu, S. & Xiang, H. Parallel delayed LMS algorithm. Sci China Ser F 44, 438–444 (2001). https://doi.org/10.1007/BF02713947
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DOI: https://doi.org/10.1007/BF02713947