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Optimizing FORTRAN programs for hierarchical memory parallel processing systems

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Abstract

Parallel loops account for the greatest amount of parallelism in numerical programs. Executing nested loops in parallel with low run-time overhead is thus very important for achieving high performance in parallel processing systems. However, in parallel processing systems with caches or local memories in memory hierarchies, “thrashing problem” may arise whenever data move back and forth between the caches or local memories in different processors.

Previous techniques can only deal with the rather simple cases with one linear function in the perfect ly nested loop. In this paper, we present a parallel program optimizing technique called hybrid loop interchange (HL1) for the cases with multiple linear functions and loop-carried data dependences in the nested loop. With HLI we can easily eliminate or reduce the thrashing phenomena without reducing the program parallelism.

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References

  1. J. Baer and W. Wang, Multilevel cache hierarchies: organizations, protocols, and performance,J. Parallel and Distributed Computing, 1989, 6(3), pp. 451–476.

    Article  Google Scholar 

  2. Z. Fang, Cache or local memory thrashing and compiler strategy in parallel processing systems. Proc. ICPP'90, St. Charles, IL, U.S.A., Aug. 13–17, 1990, pp. II271-II275.

  3. G. Jin, X. Yang and F. Chen, Loop staggering, loop compacting: Restructuring techniques for thrashing problem.J. of computer Science and Technology, 1993, 8(1), pp. 49–57.

    Article  Google Scholar 

  4. J. R. Allen and K. Kenedy, Automatic loop interchange,ACM SIGPLAN Notice, 1984, 19 (6), pp. 233–246.

    Article  Google Scholar 

  5. M. Wolfe, Advanced loop interchange. Proc. ICPP'86, St. Charles IL, U. S. A., Aug. 19–22, 1986, pp. 536–543.

  6. M. Wolfe, Optimizing supercompilers for supercomputing. Ph. D. Thesis, Univ Illinois at Urbana-Champaign, Dept. of Computer Science Rpt. No. 82-1009, 1982.

  7. C. D. Polychronopoulos, Parallel Programming and Compilers. Kluwer Academic Publishers, Boston, U. S. A. 1988.

    MATH  Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science, Changsha Institute of Technology, 410073, Changsha

    Guohua Jin & Fujie Chen

Authors
  1. Guohua Jin
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  2. Fujie Chen
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Jin, G., Chen, F. Optimizing FORTRAN programs for hierarchical memory parallel processing systems. J. of Compt. Sci. & Technol. 8, 209–220 (1993). https://doi.org/10.1007/BF02939528

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  • DOI: https://doi.org/10.1007/BF02939528

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